umull

Unsigned Multiply Long

UMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts>

Multiplies unsigned narrow vectors, producing wider result.

Pseudocode Operation

for i = 0 to (128 >> (size+1)) - 1 do
  op1 ← ZeroExtend(Vn[i], element_width)
  op2 ← ZeroExtend(Vm[i], element_width)
  Vd[i] ← op1 * op2
end for

Example

UMULL v0.4s.Td, v1.4s.Ts, v2.4s.Ts

Encoding

Binary Layout

0

31

Q

30

1

29

01110

28:24

size

23:22

1

21

Rm

20:16

1100

15:12

00

11:10

Rn

9:5

Rd

4:0

 

Format SIMD Three Register Diff

Opcode 0x2E20C000

Extension NEON (SIMD)

Operands

• Vd
  Dest (Wide)
• Vn
  First source SIMD/FP vector register
• Vm
  Second source SIMD/FP vector register

Related

Other forms of umull

• umull Unsigned Multiply Long (Thumb)
• umull Unsigned Multiply Long (A32)

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2F00A000	UMULL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]		A64		0 | Q | 1 | 01111 | size | L | M | Rm | 1010 | H | 0 | Rn | Rd
0x2E20C000	UMULL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>		A64		0 | Q | 1 | 01110 | size | 1 | Rm | 1100 | 00 | Rn | Rd
0x9BA07C00	UMULL <Xd>, <Wn>, <Wm>		A64		1 | 00 | 11011 | 1 | 01 | Rm | 0 | 11111 | Rn | Rd

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values. The UMULL instruction extracts each source vector from the lower half of each source register. The UMULL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part, datasize];
bits(datasize) operand2 = Vpart[m, part, datasize];
bits(2*datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;

V[d, 2*datasize] = result;