vaddhn

Vector Add High Narrow

VADDHN<c>.<dt> <Dd>, <Qn>, <Qm>

Adds 2N-bit elements, selects high N-bits for result.

Details

Adds corresponding 2N-bit elements from two 128-bit NEON registers, then selects the high N bits of each result and stores them as N-bit elements in the destination 64-bit register. This instruction performs unsigned or signed addition at 2× the element width, then narrows the result. No flags are affected.

Pseudocode Operation

for i = 0 to pairs-1
  Dd[i] ← (Qn[i] + Qm[i])[2*N-1:N]

Example

VADDHN.dt d0, q1, q2

Encoding

Binary Layout
1111001
0
1
D
size
Vn
Vd
0100
N
0
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2800400
Extension NEON (SIMD)

Operands

  • Dd
    Dest Narrow
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800400 VADDHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm> A32 1111001 | 0 | 1 | D | size | Vn | Vd | 0100 | N | 0 | M | 0 | Vm
0xEF800400 VADDHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm> T32 111 | 0 | 11111 | D | size | Vn | Vd | 0100 | N | 0 | M | 0 | Vm

Description

Vector Add and Narrow, returning High Half adds corresponding elements in two quadword vectors, and places the most significant half of each result in a doubleword vector. The results are truncated. For rounded results, see VRADDHN. The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        result = Elem[Qin[n>>1],e,2*esize] + Elem[Qin[m>>1],e,2*esize];
        Elem[D[d],e,esize] = result<2*esize-1:esize>;