str

Store Register (Immediate)

STR <Wt>, [<Xn|SP>, #<pimm>]

Stores a register to memory (Immediate offset).

Details

Stores a 32-bit register to memory at an address calculated from a base register and a positive immediate offset (scaled by 4). Does not affect condition flags. AArch64-only instruction; the immediate is encoded as imm12 and scaled by 4.

Pseudocode Operation

address ← Xn + (imm12 << 2)
[address] ← Wt[31:0]

Example

STR w3, [x1, #16]

Encoding

Binary Layout
10
111
0
01
00
imm12
Rn
Rt
 
Format Load/Store Imm
Opcode 0xB9000000
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • pimm
    Positive immediate offset

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x3C000400 STR <Bt>, [<Xn|SP>], #<simm> A64 00 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0x7C000400 STR <Ht>, [<Xn|SP>], #<simm> A64 01 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0xBC000400 STR <St>, [<Xn|SP>], #<simm> A64 10 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0xFC000400 STR <Dt>, [<Xn|SP>], #<simm> A64 11 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0x3C800400 STR <Qt>, [<Xn|SP>], #<simm> A64 00 | 111 | 1 | 00 | 10 | 0 | imm9 | 01 | Rn | Rt
0x3C000C00 STR <Bt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0x7C000C00 STR <Ht>, [<Xn|SP>, #<simm>]! A64 01 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0xBC000C00 STR <St>, [<Xn|SP>, #<simm>]! A64 10 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0xFC000C00 STR <Dt>, [<Xn|SP>, #<simm>]! A64 11 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0x3C800C00 STR <Qt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 1 | 00 | 10 | 0 | imm9 | 11 | Rn | Rt
0x3D000000 STR <Bt>, [<Xn|SP>{, #<pimm>}] A64 00 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt
0x7D000000 STR <Ht>, [<Xn|SP>{, #<pimm>}] A64 01 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt
0xBD000000 STR <St>, [<Xn|SP>{, #<pimm>}] A64 10 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt
0xFD000000 STR <Dt>, [<Xn|SP>{, #<pimm>}] A64 11 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt

Description

Store Register (immediate) stores a word or a doubleword from a register to memory. The address that is used for the store is calculated from a base register and an immediate offset. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(datasize) data;

boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

if !postindex then
    address = GenerateAddress(address, offset, accdesc);

if rt_unknown then
    data = bits(datasize) UNKNOWN;
else
    data = X[t, datasize];
Mem[address, datasize DIV 8, accdesc] = data;

if wback then
    if postindex then
        address = GenerateAddress(address, offset, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;