vrsubhn
Vector Rounding Subtract High Narrow
Subtracts wide elements, rounds, and returns high narrow half.
Pseudocode Operation
for i = 0 to (128 / (esize * 2) - 1)
diff ← Qn[i] - Qm[i]
rounded ← diff + (1 << (esize - 1))
Dd[i] ← (rounded >> esize)[esize - 1:0]Example
Encoding
Operands
-
Dd
Dest Narrow -
Qn
First source 128-bit SIMD register -
Qm
Second source 128-bit SIMD register
Related
More in NEON (SIMD)
Reference
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xF3800600 | VRSUBHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm> | A32 | 1111001 | 1 | 1 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm | ||
| 0xFF800600 | VRSUBHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm> | T32 | 111 | 1 | 11111 | D | size | Vn | Vd | 0110 | N | 0 | M | 0 | Vm |
Description
Vector Rounding Subtract and Narrow, returning High Half subtracts the elements of one quadword vector from the corresponding elements of another quadword vector, takes the most significant half of each result, and places the final results in a doubleword vector. The results are rounded. For truncated results, see VSUBHN. The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
round_const = 1 << (esize-1);
for e = 0 to elements-1
result = (Elem[Qin[n>>1],e,2*esize] - Elem[Qin[m>>1],e,2*esize]) + round_const;
Elem[D[d],e,esize] = result<2*esize-1:esize>;