usmmla

Unsigned-Signed Matrix Multiply-Accumulate (NEON)

USMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Matrix multiply Unsigned Int8 with Signed Int8.

Details

Performs an unsigned-signed 8-bit integer matrix multiply-accumulate operation, multiplying unsigned Int8 elements from Vn with signed Int8 elements from Vm and accumulating the results into Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM (Advanced SIMD and Floating-point Extension 2) architectural feature. No condition flags are affected; this is an AArch64-only instruction.

Pseudocode Operation

for e = 0 to (128 / 32) - 1
  Vd[e] ← Vd[e] + (Vn[4×e:4×e+3] × Vm[4×e:4×e+3])
  // Each element is 32-bit int32, products of 4×uint8 × 4×sint8

Example

USMMLA v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
1
0
01110
10
0
Rm
1010
1
1
Rn
Rd
 
Format NEON 3-Reg
Opcode 0x4E80AC00
Extension FEAT_I8MM (AI)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    Unsigned
  • Vm
    Signed

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x4E80AC00 USMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B A64 0 | 1 | 0 | 01110 | 10 | 0 | Rm | 1010 | 1 | 1 | Rn | Rd
0x45809800 USMMLA <Zda>.S, <Zn>.B, <Zm>.B A64 01000101 | 1 | 0 | 0 | Zm | 100110 | Zn | Zda

Description

Unsigned and signed 8-bit integer matrix multiply-accumulate. This instruction multiplies the 2x8 matrix of unsigned 8-bit integer values in the first source vector by the 8x2 matrix of signed 8-bit integer values in the second source vector. The resulting 2x2 32-bit integer matrix product is destructively added to the 32-bit integer matrix accumulator in the destination vector. This is equivalent to performing an 8-way dot product per destination element. From Armv8.2 to Armv8.5, this is an OPTIONAL instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.

Operation

CheckFPAdvSIMDEnabled64();
bits(128) operand1 = V[n, 128];
bits(128) operand2 = V[m, 128];
bits(128) addend = V[d, 128];

V[d, 128] = MatMulAdd(addend, operand1, operand2, TRUE, FALSE);