sha512su0

SHA512 Schedule Update 0 (A32)

SHA512SU0.64 <Qd>, <Qm>

SHA512 schedule update instruction 0.

Details

Performs the first schedule update operation for SHA-512 message scheduling, processing Qm and updating Qd with the first sigma operation. This is a unary operation used during SHA-512 preprocessing of the message schedule. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.

Pseudocode Operation

Qd ← SHA512_SU_0(Qm)

Example

SHA512SU0.64 q0, q2

Encoding

Binary Layout
11001110110000001000
00
Rn
Rd
 
Format Crypto 2-Reg
Opcode 0xCEC08000
Extension Crypto (SHA512)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xCEC08000 SHA512SU0 <Vd>.2D, <Vn>.2D A64 11001110110000001000 | 00 | Rn | Rd

Description

SHA512 Schedule Update 0 takes the values from the two 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the gamma0 functions of two iterations of the SHA512 schedule update that are performed after the first 16 iterations within a block. It returns this value to the destination SIMD&FP register. This instruction is implemented only when FEAT_SHA512 is implemented.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(64) sig0;
bits(128) Vtmp;
bits(128) x = V[n, 128];
bits(128) w = V[d, 128];
sig0 = ROR(w<127:64>, 1) EOR ROR(w<127:64>, 8) EOR ('0000000':w<127:71>);
Vtmp<63:0> = w<63:0> + sig0;
sig0 = ROR(x<63:0>, 1) EOR ROR(x<63:0>, 8) EOR ('0000000':x<63:7>);
Vtmp<127:64> = w<127:64> + sig0;
V[d, 128] = Vtmp;