stg
Store Allocation Tag
STG <Xt|SP>, [<Xn|SP>, #<simm>]
Stores the Allocation Tag to memory.
Details
Stores the Allocation Tag from Xt (bits [59:56]) into the tag storage of a 16-byte granule at address [Xn + simm]. This instruction is only available in AArch64 and requires the MTE feature. The simm9 immediate is scaled by 16. Data in the granule is not modified. No condition flags are affected.
Pseudocode Operation
address ← Xn + (simm << 4) // simm is a signed 9-bit value, scaled by 16
tag_to_store ← (Xt >> 56) & 0xF
store_tag_to_memory(address, tag_to_store)
Example
STG Xt, [x1, #-8]
Encoding
Binary Layout
11011001
00
1
imm9
01
Xn
Xt
Operands
-
Xt
Tag Src -
Xn
First source / base 64-bit integer register -
simm
Signed immediate offset
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xD9200400 | STG <Xt|SP>, [<Xn|SP>], #<simm> | A64 | 11011001 | 00 | 1 | imm9 | 01 | Xn | Xt | ||
| 0xD9200C00 | STG <Xt|SP>, [<Xn|SP>, #<simm>]! | A64 | 11011001 | 00 | 1 | imm9 | 11 | Xn | Xt | ||
| 0xD9200800 | STG <Xt|SP>, [<Xn|SP>{, #<simm>}] | A64 | 11011001 | 00 | 1 | imm9 | 10 | Xn | Xt |
Description
Store Allocation Tag stores an Allocation Tag to memory. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag granule. The Allocation Tag is calculated from the Logical Address Tag in the source register.
This instruction generates an Unchecked access.
Operation
bits(64) address;
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n, 64];
AccessDescriptor accdesc = CreateAccDescLDGSTG(MemOp_STORE, FALSE);
if !postindex then
address = GenerateAddress(address, offset, accdesc);
bits(64) data = if t == 31 then SP[] else X[t, 64];
bits(4) tag = AArch64.AllocationTagFromAddress(data);
AArch64.MemTag[address, accdesc] = tag;
if writeback then
if postindex then
address = GenerateAddress(address, offset, accdesc);
if n == 31 then
SP[] = address;
else
X[n, 64] = address;