vrintr
Vector Round Floating-Point (Current)
VRINTR<c>.F32 <Sd>, <Sm>
Rounds float to integral float using FPSCR rounding mode.
Pseudocode Operation
rounding_mode ← FPSCR.RMode
Sd ← RoundFP(Sm, rounding_mode)
Example
VRINTR.F32 s0, s2
Encoding
Binary Layout
cond
31:28
11101
27:23
D
22
11
21:20
0
19
110
18:16
Vd
15:12
10
11:10
10
9:8
0
7
1
6
M
5
0
4
Vm
3:0
Operands
-
Sd
Destination 32-bit floating-point register -
Sm
Second source 32-bit floating-point register
Related
More in VFP (Float)
Reference
View in Arm A64 ISA Reference ↗
Arm AArch32 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0EB60940 | VRINTR{<c>}{<q>}.F16 <Sd>, <Sm> | A32 | cond | 11101 | D | 11 | 0 | 110 | Vd | 10 | 01 | 0 | 1 | M | 0 | Vm | ||
| 0x0EB60A40 | VRINTR{<c>}{<q>}.F32 <Sd>, <Sm> | A32 | cond | 11101 | D | 11 | 0 | 110 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm | ||
| 0x0EB60B40 | VRINTR{<c>}{<q>}.F64 <Dd>, <Dm> | A32 | cond | 11101 | D | 11 | 0 | 110 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm | ||
| 0xEEB60940 | VRINTR{<c>}{<q>}.F16 <Sd>, <Sm> | T32 | 111011101 | D | 11 | 0 | 110 | Vd | 10 | 01 | 0 | 1 | M | 0 | Vm | ||
| 0xEEB60A40 | VRINTR{<c>}{<q>}.F32 <Sd>, <Sm> | T32 | 111011101 | D | 11 | 0 | 110 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm | ||
| 0xEEB60B40 | VRINTR{<c>}{<q>}.F64 <Dd>, <Dm> | T32 | 111011101 | D | 11 | 0 | 110 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm |
Description
Round floating-point to integer rounds a floating-point value to an integral floating-point value of the same size using the rounding mode specified in the FPSCR. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
case esize of
when 16
S[d] = Zeros(16) : FPRoundInt(S[m]<15:0>, FPSCR[], rounding, exact);
when 32
S[d] = FPRoundInt(S[m], FPSCR[], rounding, exact);
when 64
D[d] = FPRoundInt(D[m], FPSCR[], rounding, exact);