mul

Multiply (A32)

MUL{S}<c> <Rd>, <Rn>, <Rm>

Multiplies two 32-bit values.

Pseudocode Operation

product ← Rn * Rm
Rd ← product[31:0]
if S == 1 then
  N ← Rd[31]
  Z ← (Rd == 0)
  C ← unpredictable
  V ← unpredictable

Example

MUL r0, r1, r2

Encoding

Binary Layout

cond

31:28

0000

27:24

000

23:21

19:16

0000

15:12

11:8

1001

7:4

3:0

Format Multiply

Opcode 0x00000090

Extension A32 (Base)

Operands

Rd
Destination general-purpose register
Rn
First source / base general-purpose register
Rm
Second source / offset general-purpose register

Other forms of mul

mul Vector Multiply (Integer)
mul SVE Integer Multiply (Predicated)

Across architectures

Integer Multiply : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x00000090	MUL{<c>}{<q>} <Rd>, <Rn>{, <Rm>}	A32	cond \| 0000 \| 000 \| 0 \| Rd \| 0000 \| Rm \| 1001 \| Rn
0x4340	MUL<c>{<q>} <Rdm>, <Rn>{, <Rdm>}	T32	010000 \| 1101 \| Rn \| Rdm
0xFB00F000	MUL<c>.W <Rd>, <Rn>{, <Rm>}	T32	111110110 \| 000 \| Rn \| 1111 \| Rd \| 00 \| 00 \| Rm

Description

Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the T32 instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many implementations.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    operand1 = SInt(R[n]);  // operand1 = UInt(R[n]) produces the same final results
    operand2 = SInt(R[m]);  // operand2 = UInt(R[m]) produces the same final results
    result = operand1 * operand2;
    R[d] = result<31:0>;
    if setflags then
        PSTATE.N = result<31>;
        PSTATE.Z = IsZeroBit(result<31:0>);
        // PSTATE.C, PSTATE.V unchanged

mul