mul
Multiply (A32)
MUL{S}<c> <Rd>, <Rn>, <Rm>
Multiplies two 32-bit values.
Details
Multiply computes the product of Rn and Rm and stores the low 32 bits in Rd; the high 32 bits are discarded. If the S bit is set, the N and Z flags are updated based on the result; the C and V flags are unpredictable. This is an A32 instruction available in all privilege levels.
Pseudocode Operation
product ← Rn * Rm
Rd ← product[31:0]
if S == 1 then
N ← Rd[31]
Z ← (Rd == 0)
C ← unpredictable
V ← unpredictable
Example
MUL r0, r1, r2
Encoding
Binary Layout
cond
0000
000
0
Rd
0000
Rm
1001
Rn
Operands
-
Rd
Destination general-purpose register -
Rn
First source / base general-purpose register -
Rm
Second source / offset general-purpose register
Reference (Arm AArch32 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x00000090 | MUL{<c>}{<q>} <Rd>, <Rn>{, <Rm>} | A32 | cond | 0000 | 000 | 0 | Rd | 0000 | Rm | 1001 | Rn | ||
| 0x4340 | MUL<c>{<q>} <Rdm>, <Rn>{, <Rdm>} | T32 | 010000 | 1101 | Rn | Rdm | ||
| 0xFB00F000 | MUL<c>.W <Rd>, <Rn>{, <Rm>} | T32 | 111110110 | 000 | Rn | 1111 | Rd | 00 | 00 | Rm |
Description
Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values.
Optionally, it can update the condition flags based on the result. In the T32 instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many implementations.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results
operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results
result = operand1 * operand2;
R[d] = result<31:0>;
if setflags then
PSTATE.N = result<31>;
PSTATE.Z = IsZeroBit(result<31:0>);
// PSTATE.C, PSTATE.V unchanged