ldaexd

Load Acquire Exclusive Double (A32)

LDAEXD<c> <Rt>, <Rt2>, [<Rn>]

Loads a doubleword, acquires semantics, marks exclusive.

Pseudocode Operation

Rt ← [Rn]; Rt2 ← [Rn+4]; ExclusiveLocal ← TRUE; Acquire()

Example

LDAEXD r3, r4, [r1]

Encoding

Binary Layout

cond

31:28

00011

27:23

01

22:21

1

20

Rn

19:16

Rt

15:12

1

11

1

10

1

9

0

8

1001

7:4

1111

3:0

 

Format Load Excl

Opcode 0x01B00E9F

Extension A32 (Atomic)

Operands

• Rt
  Dest 1
• Rt2
  Dest 2
• Rn
  First source / base general-purpose register

Related

More in A32 (Atomic)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x01B00E9F	LDAEXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]		A32		cond | 00011 | 01 | 1 | Rn | Rt | 1 | 1 | 1 | 0 | 1001 | 1111
0xE8D000FF	LDAEXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]		T32		11101000110 | 1 | Rn | Rt | Rt2 | 1 | 1 | 11 | 1111

Description

Load-Acquire Exclusive Doubleword loads a doubleword from memory, writes it to two registers and: The instruction also acts as a barrier instruction with the ordering requirements described in Load-Acquire, Store-Release. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    AArch32.SetExclusiveMonitors(address, 8);
    value = MemO[address, 8];
    // Extract words from 64-bit loaded value such that R[t] is
    // loaded from address and R[t2] from address+4.
    R[t]  = if BigEndian(AccessType_GPR) then value<63:32> else value<31:0>;
    R[t2] = if BigEndian(AccessType_GPR) then value<31:0>  else value<63:32>;