sha1h

SHA1 Hash Update (A32)

SHA1H.32 <Qd>, <Qm>

Updates SHA1 hash state.

Details

SHA1 Hash Update: performs the final hash update step in the SHA1 algorithm by processing the hash state. This instruction computes the SHA1 hash finalization on four 32-bit words in parallel. No condition flags are affected. Available in A32 and T32 with Crypto extension support.

Pseudocode Operation

Qd[127:96] ← ROTATE_LEFT(Qm[127:96], 30)
Qd[95:64] ← ROTATE_LEFT(Qm[95:64], 30)
Qd[63:32] ← ROTATE_LEFT(Qm[63:32], 30)
Qd[31:0] ← ROTATE_LEFT(Qm[31:0], 30)

Example

SHA1H.32 q0, q2

Encoding

Binary Layout
11110011
1
D
11
10
10
Vd
00000
Q
M
1
Vm
 
Format Crypto 2-Reg
Opcode 0xF3B102C0
Extension Crypto

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5E280800 SHA1H <Sd>, <Sn> A64 01011110 | 00 | 10100 | 00000 | 10 | Rn | Rd

Description

SHA1 fixed rotate.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(32) operand = V[n, 32];    // read element [0] only,  [1-3] zeroed
V[d, 32] = ROL(operand, 30);