trn1

SVE Transpose 1

TRN1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

Interleaves even elements from two vectors.

Pseudocode Operation

integer esize = 8 << UInt(sz);
integer elements = VL / esize;
for e = 0 to elements-1
  integer src_index = 2 * e;
  if src_index < elements then
    Zd[e * esize +: esize] = Zn[src_index * esize +: esize];
  else
    Zd[e * esize +: esize] = Zm[(src_index - elements) * esize +: esize];

Example

TRN1 z0.s.T, z1.s.T, z2.s.T

Encoding

Binary Layout

00000101

31:24

size

23:22

1

21

Zm

20:16

011

15:13

10

12:11

0

10

Zn

9:5

Zd

4:0

 

Format SVE Permute

Opcode 0x05207000

Extension SVE

Operands

• Zd
  Destination scalable vector register (SVE)
• Zn
  First source scalable vector register (SVE)
• Zm
  Second source scalable vector register (SVE)

Related

Other forms of trn1

• trn1 Vector Transpose 1

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0E002800	TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 | Q | 001110 | size | 0 | Rm | 0 | 0 | 1010 | Rn | Rd
0x05205000	TRN1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>		A64		00000101 | size | 10 | Pm | 010 | 1 | 0 | 0 | 0 | Pn | 0 | Pd
0x05207000	TRN1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>		A64		00000101 | size | 1 | Zm | 011 | 10 | 0 | Zn | Zd
0x05A01800	TRN1 <Zd>.Q, <Zn>.Q, <Zm>.Q		A64		00000101101 | Zm | 000 | 1 | 1 | 0 | Zn | Zd

Description

Interleave alternating even or odd-numbered elements from the first and second source vectors and place in elements of the destination vector. This instruction is unpredicated. The 128-bit element variant requires that the Effective SVE vector length is at least 256 bits. ID_AA64ZFR0_EL1.F64MM indicates whether the 128-bit element variant is implemented. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
if VL < esize * 2 then UNDEFINED;
constant integer pairs = VL DIV (esize * 2);
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result = Zeros(VL);

for p = 0 to pairs-1
    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];

Z[d, VL] = result;