ldtr

Load Register (Unprivileged)

LDTR <Wt>, [<Xn|SP>, #<simm>]

Loads a word as if in EL0 (User mode).

Details

Loads a 32-bit word from memory using an address calculated from a base register and a signed immediate offset, with the access performed as if executing at EL0 (User mode) privilege level. This instruction is typically used for debugging or privilege crossing and does not affect condition flags (N, Z, C, V remain unaffected). Execution is AArch64-only and restricted to privileged exception levels (EL1 or higher); using it at EL0 results in an illegal instruction exception.

Pseudocode Operation

address ← (Xn | SP) + SignExtend(imm9, 64); Wt ← ZeroExtend([address]<31:0>, 64)

Example

LDTR w3, [x1, #-8]

Encoding

Binary Layout
10
111
0
00
01
0
imm9
10
Rn
Rt
 
Format Load/Store
Opcode 0xB8400800
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • simm
    Signed immediate offset

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xB8400800 LDTR <Wt>, [<Xn|SP>{, #<simm>}] A64 10 | 111 | 0 | 00 | 01 | 0 | imm9 | 10 | Rn | Rt
0xF8400800 LDTR <Xt>, [<Xn|SP>{, #<simm>}] A64 11 | 111 | 0 | 00 | 01 | 0 | imm9 | 10 | Rn | Rt

Description

Load Register (unprivileged) loads a word or doubleword from memory, and writes it to a register. The address that is used for the load is calculated from a base register and an immediate offset. Memory accesses made by the instruction behave as if the instruction was executed at EL0 if the Effective value of PSTATE.UAO is 0 and either: Otherwise, the memory access operates with the restrictions determined by the Exception level at which the instruction is executed. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(datasize) data;

boolean privileged = AArch64.IsUnprivAccessPriv();
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, FALSE, privileged, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, offset, accdesc);

data = Mem[address, datasize DIV 8, accdesc];
X[t, regsize] = ZeroExtend(data, regsize);