vtst

Vector Test Bits

VTST<c>.<dt> <Qd>, <Qn>, <Qm>

Tests if any bits match (Vd = (Vn & Vm) != 0).

Details

The Vector Test Bits instruction tests if any bits match (Vd = (Vn & Vm) != 0).

Pseudocode Operation

// Tests if any bits match (Vd = (Vn & Vm) != 0)

Example

VTST.dt q0, q1, q2

Encoding

Binary Layout
11110010
0
sz
0
Vn
Vd
1000
N
Q
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2000810
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register