vtst

Vector Test Bits

VTST<c>.<dt> <Qd>, <Qn>, <Qm>

Tests if any bits match (Vd = (Vn & Vm) != 0).

Pseudocode Operation

for i ← 0 to (128 / element_width) - 1:
  result ← Qn[i * element_width +: element_width] AND Qm[i * element_width +: element_width]
  if result != 0:
    Qd[i * element_width +: element_width] ← (element_width bits of 1s)
  else:
    Qd[i * element_width +: element_width] ← 0

Example

VTST.dt q0, q1, q2

Encoding

Binary Layout
1111001
31:25
0
24
0
23
D
22
size
21:20
Vn
19:16
Vd
15:12
1000
11:8
N
7
0
6
M
5
1
4
Vm
3:0
 
Format NEON 3-Reg
Opcode 0xF2000810
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2000810 VTST{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm> A32 1111001 | 0 | 0 | D | size | Vn | Vd | 1000 | N | 0 | M | 1 | Vm
0xF2000850 VTST{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Qm> A32 1111001 | 0 | 0 | D | size | Vn | Vd | 1000 | N | 1 | M | 1 | Vm
0xEF000810 VTST{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm> T32 111 | 0 | 11110 | D | size | Vn | Vd | 1000 | N | 0 | M | 1 | Vm
0xEF000850 VTST{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Qm> T32 111 | 0 | 11110 | D | size | Vn | Vd | 1000 | N | 1 | M | 1 | Vm

Description

Vector Test Bits takes each element in a vector, and bitwise ANDs it with the corresponding element of a second vector. If the result is not zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros. The operand vector elements can be any one of: The result vector elements are fields the same size as the operand vector elements. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            if !IsZero(Elem[D[n+r],e,esize] AND Elem[D[m+r],e,esize]) then
                Elem[D[d+r],e,esize] = Ones(esize);
            else
                Elem[D[d+r],e,esize] = Zeros(esize);