and

Bitwise AND (A32)

AND{S}<c> <Rd>, <Rn>, <Rm> {, <shift>}

Performs a bitwise AND on two 32-bit values.

Details

Performs a bitwise AND of two 32-bit values and stores the result in Rd. If the S suffix is present, condition flags are updated: N and Z are set based on the result, C is set to the shifter carry-out, and V is unaffected. Executes in A32 (32-bit ARM) instruction set only.

Pseudocode Operation

result ← Rn AND (Rm shifted by shift_amount)
Rd ← result
if S == 1 then
  N ← result[31]
  Z ← (result == 0)
  C ← shifter_carry_out
else
  condition_flags unchanged

Example

AND r0, r1, r2

Encoding

Binary Layout
cond
0000
000
0
Rn
Rd
imm5
stype
0
Rm
 
Format Data Proc
Opcode 0x00000000
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x02000000 AND{<c>}{<q>} {<Rd>,} <Rn>, #<const> A32 cond | 0010 | 000 | 0 | Rn | Rd | imm12
0xF0000000 AND{<c>}{<q>} {<Rd>,} <Rn>, #<const> T32 11110 | i | 0 | 0000 | 0 | Rn | 0 | imm3 | Rd | imm8
0x00000060 AND{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX A32 cond | 0000 | 000 | 0 | Rn | Rd | 00000 | 11 | 0 | Rm
0x00000000 AND{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} A32 cond | 0000 | 000 | 0 | Rn | Rd | imm5 | stype | 0 | Rm
0x4000 AND<c>{<q>} {<Rdn>,} <Rdn>, <Rm> T32 010000 | 0000 | Rm | Rdn
0xEA000030 AND{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX T32 1110101 | 0000 | 0 | Rn | 0 | 000 | Rd | 00 | 11 | Rm
0xEA000000 AND<c>.W {<Rd>,} <Rn>, <Rm> T32 1110101 | 0000 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm
0x00000010 AND{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> A32 cond | 0000 | 000 | 0 | Rn | Rd | Rs | 0 | stype | 1 | Rm

Description

Bitwise AND (register) performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. If the destination register is not the PC, the ANDS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
    result = R[n] AND shifted;
    if d == 15 then          // Can only occur for A32 encoding
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.N = result<31>;
            PSTATE.Z = IsZeroBit(result);
            PSTATE.C = carry;
            // PSTATE.V unchanged