vfms
Vector Fused Multiply Subtract
VFMS<c>.F32 <Qd>, <Qn>, <Qm>
Computes Vd = Vd - (Vn * Vm) with single rounding.
Pseudocode Operation
for i = 0 to 3 do
Qd[i] ← round_to_nearest(Qd[i] - (Qn[i] × Qm[i]))Example
VFMS.F32 q0, q1, q2
Encoding
Binary Layout
1111001
31:25
0
24
0
23
D
22
1
21
sz
20
Vn
19:16
Vd
15:12
1100
11:8
N
7
0
6
M
5
1
4
Vm
3:0
Operands
-
Qd
Dest/Acc -
Qn
First source 128-bit SIMD register -
Qm
Second source 128-bit SIMD register
Reference
View in Arm A64 ISA Reference ↗
Arm AArch32 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xF2200C10 | VFMS{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> | A32 | 1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1100 | N | 0 | M | 1 | Vm | ||
| 0xF2200C50 | VFMS{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> | A32 | 1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1100 | N | 1 | M | 1 | Vm | ||
| 0x0EA00940 | VFMS{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> | A32 | cond | 1110 | 1 | D | 10 | Vn | Vd | 10 | 01 | N | 1 | M | 0 | Vm | ||
| 0x0EA00A40 | VFMS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> | A32 | cond | 1110 | 1 | D | 10 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm | ||
| 0x0EA00B40 | VFMS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> | A32 | cond | 1110 | 1 | D | 10 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm | ||
| 0xEF200C10 | VFMS{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm> | T32 | 111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1100 | N | 0 | M | 1 | Vm | ||
| 0xEF200C50 | VFMS{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm> | T32 | 111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1100 | N | 1 | M | 1 | Vm | ||
| 0xEEA00940 | VFMS{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> | T32 | 11101110 | 1 | D | 10 | Vn | Vd | 10 | 01 | N | 1 | M | 0 | Vm | ||
| 0xEEA00A40 | VFMS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> | T32 | 11101110 | 1 | D | 10 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm | ||
| 0xEEA00B40 | VFMS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> | T32 | 11101110 | 1 | D | 10 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm |
Description
Vector Fused Multiply Subtract negates the elements of one vector and multiplies them with the corresponding elements of another vector, adds the products to the corresponding elements of the destination vector, and places the results in the destination vector. The instruction does not round the result of the multiply before the addition. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
if advsimd then // Advanced SIMD instruction
for r = 0 to regs-1
for e = 0 to elements-1
bits(esize) op1 = Elem[D[n+r],e,esize];
if op1_neg then op1 = FPNeg(op1);
Elem[D[d+r],e,esize] = FPMulAdd(Elem[D[d+r],e,esize],
op1, Elem[D[m+r],e,esize], StandardFPSCRValue());
else // VFP instruction
case esize of
when 16
op16 = if op1_neg then FPNeg(S[n]<15:0>) else S[n]<15:0>;
S[d] = Zeros(16) : FPMulAdd(S[d]<15:0>, op16, S[m]<15:0>, FPSCR[]);
when 32
op32 = if op1_neg then FPNeg(S[n]) else S[n];
S[d] = FPMulAdd(S[d], op32, S[m], FPSCR[]);
when 64
op64 = if op1_neg then FPNeg(D[n]) else D[n];
D[d] = FPMulAdd(D[d], op64, D[m], FPSCR[]);