vbsl

Vector Bit Select

VBSL<c> <Qd>, <Qn>, <Qm>

Selects bits from Vn or Vm based on Vd (mask).

Pseudocode Operation

for i = 0 to 127
  if Qd[i] == 1 then Qd[i] ← Qn[i] else Qd[i] ← Qm[i]

Example

VBSL q0, q1, q2

Encoding

Binary Layout

1111001

31:25

1

24

0

23

D

22

01

21:20

Vn

19:16

Vd

15:12

0001

11:8

N

7

0

6

M

5

1

4

Vm

3:0

 

Format NEON 3-Reg

Opcode 0xF3100110

Extension NEON (SIMD)

Operands

• Qd
  Dest/Mask
• Qn
  First source 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF3100110	VBSL{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>		A32		1111001 | 1 | 0 | D | 01 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xF3100150	VBSL{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>		A32		1111001 | 1 | 0 | D | 01 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm
0xFF100110	VBSL{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>		T32		111 | 1 | 11110 | D | 01 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xFF100150	VBSL{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>		T32		111 | 1 | 11110 | D | 01 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm

Description

Vector Bitwise Select sets each bit in the destination to the corresponding bit from the first source operand when the original destination bit was 1, otherwise from the second source operand. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        case operation of
            when VBitOps_VBIF  D[d+r] = (D[d+r] AND D[m+r]) OR (D[n+r] AND NOT(D[m+r]));
            when VBitOps_VBIT  D[d+r] = (D[n+r] AND D[m+r]) OR (D[d+r] AND NOT(D[m+r]));
            when VBitOps_VBSL  D[d+r] = (D[n+r] AND D[d+r]) OR (D[m+r] AND NOT(D[d+r]));