st64bv0

Single-copy Atomic 64-byte Store with Return (Zero)

ST64BV0 <Ws>, <Xt>, [<Xn|SP>]

Stores 64 bytes (eliding the first 8 bytes as zero) and returns status.

Pseudocode Operation

address ← Xn|SP; if address<5:0> != 0 then Fault(Alignment); data<63:0> ← 0; data<511:64> ← [Xt+1, Xt+2, ..., Xt+7]<447:0>; success ← AtomicStore64B(address, data); Ws ← if success then 0 else implementation_defined_nonzero;

Example

ST64BV0 w6, x3, [x1]

Encoding

Binary Layout
11
31:30
111
29:27
0
26
00
25:24
0
23
0
22
1
21
Rs
20:16
1
15
010
14:12
00
11:10
Rn
9:5
Rt
4:0
 
Format Load/Store
Opcode 0xF820A000
Extension LSE (Atomics)

Operands

  • Ws
    Status
  • Xt
    Data
  • Xn
    First source / base 64-bit integer register

Related

More in LSE (Atomics)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF820A000 ST64BV0 <Xs>, <Xt>, [<Xn|SP>] A64 11 | 111 | 0 | 00 | 0 | 0 | 1 | Rs | 1 | 010 | 00 | Rn | Rt

Description

Single-copy Atomic 64-byte EL0 Store with status result stores eight 64-bit doublewords from consecutive registers, Xt to X(t+7), to a memory location, with the bottom 32 bits taken from ACCDATA_EL1, and writes the status result of the store to a register. The data that is stored is atomic and is required to be 64-byte aligned.

Operation

CheckST64BV0Enabled();

bits(512) data;
bits(64) address;
bits(64) value;
bits(64) status;

AccessDescriptor accdesc = CreateAccDescLS64(memop, tagchecked);
bits(64) Xt = X[t, 64];
value<31:0> = ACCDATA_EL1<31:0>;
value<63:32> = Xt<63:32>;
if BigEndian(accdesc.acctype) then value = BigEndianReverse(value);
data<63:0> = value;
for i = 1 to 7
    value = X[t+i, 64];
    if BigEndian(accdesc.acctype) then value = BigEndianReverse(value);
    data<63+64*i:64*i> = value;

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

status = MemStore64BWithRet(address, data, accdesc);

if s != 31 then X[s, 64] = status;