frint64z
Floating-Point Round to 64-bit Integer (Zero)
FRINT64Z <Sd>, <Sn>
Rounds to 64-bit integer towards zero.
Details
Rounds the source single-precision floating-point value to a 64-bit signed integer using round towards zero (truncate) rounding mode, and writes the result as a single-precision floating-point value to the destination. Does not update the NZCV condition flags. Requires FEAT_FRINTTS extension; AArch64 only.
Pseudocode Operation
Xn_bits ← Sn
int64_val ← RoundTowardsZero(FPUnpack(Xn_bits), 64)
Sd ← FPPack(int64_val as single-precision floating-point)Example
FRINT64Z s0, s1
Encoding
Binary Layout
0
0
0
11110
00
10100
10
10000
Rn
Rd
Operands
-
Sd
Destination 32-bit floating-point register -
Sn
First source 32-bit floating-point register
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0E21F800 | FRINT64Z <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 0 | 011100 | sz | 100001111 | 1 | 10 | Rn | Rd | ||
| 0x1E294000 | FRINT64Z <Sd>, <Sn> | A64 | 0 | 0 | 0 | 11110 | 00 | 10100 | 10 | 10000 | Rn | Rd | ||
| 0x1E694000 | FRINT64Z <Dd>, <Dn> | A64 | 0 | 0 | 0 | 11110 | 01 | 10100 | 10 | 10000 | Rn | Rd |
Description
Floating-point Round to 64-bit Integer toward Zero (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value that fits into a 64-bit integer size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.
A zero input returns a zero result with the same sign. When the result value is not numerically equal to the {corresponding} input value, an Inexact exception is raised. When the input is infinite, NaN or out-of-range, the instruction returns {for the corresponding result value} the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPEnabled64(); boolean merge = IsMerging(FPCR); bits(128) result = if merge then V[d, 128] else Zeros(128); bits(esize) operand = V[n, esize]; Elem[result, 0, esize] = FPRoundIntN(operand, FPCR, FPRounding_ZERO, intsize); V[d, 128] = result;