udot
Unsigned Dot Product (NEON)
UDOT <Vd>.4S, <Vn>.16B, <Vm>.16B
Dot product of unsigned integers (AArch64 NEON).
Details
Unsigned dot product of 16 bytes viewed as 4 groups of 4 unsigned bytes, accumulating 32-bit unsigned integer results into Vd. Computes Vd[i] = Vd[i] + (Vn[4i] × Vm[4i]) + (Vn[4i+1] × Vm[4i+1]) + (Vn[4i+2] × Vm[4i+2]) + (Vn[4i+3] × Vm[4i+3]) for each 32-bit lane. Requires FEAT_DotProd. Condition flags are not affected.
Pseudocode Operation
Example
UDOT v0.4s.4S, v1.4s.16B, v2.4s.16B
Encoding
Binary Layout
0
Q
1
01110
size
0
Rm
1
0010
1
Rn
Rd
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
First source SIMD/FP vector register -
Vm
Second source SIMD/FP vector register
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x2F00E000 | UDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] | A64 | 0 | Q | 1 | 01111 | size | L | M | Rm | 1110 | H | 0 | Rn | Rd | ||
| 0x2E009400 | UDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> | A64 | 0 | Q | 1 | 01110 | size | 0 | Rm | 1 | 0010 | 1 | Rn | Rd | ||
| 0x4400CC00 | UDOT <Zda>.S, <Zn>.H, <Zm>.H | A64 | 01000100000 | Zm | 11001 | 1 | Zn | Zda | ||
| 0x4480CC00 | UDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] | A64 | 01000100100 | i2 | Zm | 11001 | 1 | Zn | Zda | ||
| 0x44000400 | UDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> | A64 | 01000100 | size | 0 | Zm | 00000 | 1 | Zn | Zda | ||
| 0x44A00400 | UDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] | A64 | 01000100 | 1 | 0 | 1 | i2 | Zm | 00000 | 1 | Zn | Zda | ||
| 0x44E00400 | UDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>] | A64 | 01000100 | 1 | 1 | 1 | i1 | Zm | 00000 | 1 | Zn | Zda | ||
| 0xC1501010 | UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] | A64 | 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 0 | 1 | 0 | off3 | ||
| 0xC1509010 | UDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] | A64 | 110000010101 | Zm | 1 | Rv | 1 | i2 | Zn | 0 | 0 | 1 | 0 | off3 | ||
| 0xC1601418 | UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H | A64 | 11 | 0000010110 | Zm | 0 | Rv | 101 | Zn | 1 | 1 | off3 | ||
| 0xC1701418 | UDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H | A64 | 11 | 0000010111 | Zm | 0 | Rv | 101 | Zn | 1 | 1 | off3 | ||
| 0xC1E01418 | UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } | A64 | 11 | 000001111 | Zm | 00 | Rv | 101 | Zn | 0 | 1 | 1 | off3 | ||
| 0xC1E11418 | UDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } | A64 | 11 | 000001111 | Zm | 010 | Rv | 101 | Zn | 00 | 1 | 1 | off3 | ||
| 0xC1501030 | UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] | A64 | 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 1 | 1 | 0 | off3 |
Description
Dot Product unsigned arithmetic (vector). This instruction performs the dot product of the four unsigned 8-bit elements in each 32-bit element of the first source register with the four unsigned 8-bit elements of the corresponding 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4 it is mandatory for all implementations to support it.
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
result = V[d, datasize];
for e = 0 to elements-1
integer res = 0;
integer element1, element2;
for i = 0 to 3
if signed then
element1 = SInt(Elem[operand1, 4*e+i, esize DIV 4]);
element2 = SInt(Elem[operand2, 4*e+i, esize DIV 4]);
else
element1 = UInt(Elem[operand1, 4*e+i, esize DIV 4]);
element2 = UInt(Elem[operand2, 4*e+i, esize DIV 4]);
res = res + element1 * element2;
Elem[result, e, esize] = Elem[result, e, esize] + res;
V[d, datasize] = result;