udot

Unsigned Dot Product (Multi-vector)

UDOT { <Zd1>.S-<Zd2>.S }, <Zn>.B, <Zm>.B

Multi-vector unsigned dot product (SME2).

Details

Performs multi-vector unsigned dot product between byte elements, accumulating results into 32-bit destination registers. This SME2 instruction operates on a pair of consecutive 32-bit result registers and does not affect condition flags. Each 32-bit result accumulates the dot products of four unsigned byte multiplications.

Pseudocode Operation

for i = 0 to VL/32-1 do
  acc ← 0
  for j = 0 to 3 do
    acc ← acc + (unsigned(Zn[i*4+j]) × unsigned(Zm[i*4+j]))
  Zd[i*64 +: 32] ← Zd[i*64 +: 32] + acc
  Zd[i*64+32 +: 32] ← Zd[i*64+32 +: 32] + acc

Example

UDOT z1.s.B, z2.s.B

Encoding

Binary Layout
01000100
size
0
Zm
00000
1
Zn
Zda
 
Format SME2 DotProd
Opcode 0x44000400
Extension SME2

Operands

  • Zd
    Dest Pair
  • Zn
    First source scalable vector register (SVE)
  • Zm
    Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2F00E000 UDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] A64 0 | Q | 1 | 01111 | size | L | M | Rm | 1110 | H | 0 | Rn | Rd
0x2E009400 UDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> A64 0 | Q | 1 | 01110 | size | 0 | Rm | 1 | 0010 | 1 | Rn | Rd
0x4400CC00 UDOT <Zda>.S, <Zn>.H, <Zm>.H A64 01000100000 | Zm | 11001 | 1 | Zn | Zda
0x4480CC00 UDOT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] A64 01000100100 | i2 | Zm | 11001 | 1 | Zn | Zda
0x44000400 UDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> A64 01000100 | size | 0 | Zm | 00000 | 1 | Zn | Zda
0x44A00400 UDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] A64 01000100 | 1 | 0 | 1 | i2 | Zm | 00000 | 1 | Zn | Zda
0x44E00400 UDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>] A64 01000100 | 1 | 1 | 1 | i1 | Zm | 00000 | 1 | Zn | Zda
0xC1501010 UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] A64 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 0 | 1 | 0 | off3
0xC1509010 UDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] A64 110000010101 | Zm | 1 | Rv | 1 | i2 | Zn | 0 | 0 | 1 | 0 | off3
0xC1601418 UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H A64 11 | 0000010110 | Zm | 0 | Rv | 101 | Zn | 1 | 1 | off3
0xC1701418 UDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H A64 11 | 0000010111 | Zm | 0 | Rv | 101 | Zn | 1 | 1 | off3
0xC1E01418 UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H } A64 11 | 000001111 | Zm | 00 | Rv | 101 | Zn | 0 | 1 | 1 | off3
0xC1E11418 UDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H } A64 11 | 000001111 | Zm | 010 | Rv | 101 | Zn | 00 | 1 | 1 | off3
0xC1501030 UDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] A64 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 1 | 1 | 0 | off3

Description

The unsigned integer dot product instruction computes the dot product of a group of four unsigned 8-bit or 16-bit integer values held in each 32-bit or 64-bit element of the first source vector multiplied by a group of four unsigned 8-bit or 16-bit integer values in the corresponding 32-bit or 64-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit or 64-bit element of the destination vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) operand3 = Z[da, VL];
bits(VL) result;

for e = 0 to elements-1
    bits(esize) res = Elem[operand3, e, esize];
    for i = 0 to 3
        integer element1 = UInt(Elem[operand1, 4 * e + i, esize DIV 4]);
        integer element2 = UInt(Elem[operand2, 4 * e + i, esize DIV 4]);
        res = res + element1 * element2;
    Elem[result, e, esize] = res;

Z[da, VL] = result;