pop

Pop (Thumb)

POP <registers>

Pop registers from stack (Thumb 16-bit).

Details

Pop Registers from Stack loads multiple registers from memory addresses specified by the SP register, incrementing SP after each load. The P bit in the encoding indicates whether the PC is included in the register list. This Thumb 16-bit instruction does not affect condition flags directly but may load into the PC, which can cause a branch.

Pseudocode Operation

address ← SP
for each register in register_list (in ascending order):
  register ← [address]
  address ← address + 4
SP ← address
if P == 1 then
  PC ← [SP - 4]
  address ← address (SP already updated)

Example

POP registers

Encoding

Binary Layout
1011
1
10
P
register_list
 
Format Thumb Load Multiple
Opcode 0xBC00
Extension T32 (Base)

Operands

  • registers
    List

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xBC00 POP{<c>}{<q>} <registers> T32 1011 | 1 | 10 | P | register_list
0x08BD0000 POP{<c>}{<q>} <registers> A32 cond | 100 | 0 | 1 | 0 | 1 | 1 | 1101 | register_list
0xE8BD0000 POP{<c>}.W <registers> T32 1110100 | 01 | 0 | 1 | 1 | 1101 | P | M | register_list
0x049D0004 POP{<c>}{<q>} <single_register_list> A32 cond | 010 | 0 | 1 | 0 | 0 | 1 | 1101 | Rt | 000000000100
0xF85D0B04 POP{<c>}{<q>} <single_register_list> T32 111110000 | 10 | 1 | 1101 | Rt | 1 | 0 | 1 | 1 | 00000100

Description

Pop Multiple Registers from Stack loads multiple general-purpose registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also Encoding of lists of general-purpose registers and the PC. The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[13];
    for i = 0 to 14
        if registers<i> == '1' then
            R[i] = if UnalignedAllowed then MemU[address,4] else MemA[address,4];
            address = address + 4;
    if registers<15> == '1' then
        if UnalignedAllowed then
            if address<1:0> == '00' then
                LoadWritePC(MemU[address,4]);
            else
                UNPREDICTABLE;
        else
            LoadWritePC(MemA[address,4]);
    if registers<13> == '0' then R[13] = R[13] + 4*BitCount(registers);
    if registers<13> == '1' then R[13] = bits(32) UNKNOWN;