movw

Move Word (A32)

MOVW<c> <Rd>, #<imm16>

Writes a 16-bit immediate to the bottom half, zeroing top.

Details

Move Word writes a 16-bit immediate value into bits [15:0] of Rd and zeros bits [31:16]. No condition flags are affected. This is an A32 instruction (ARMv6T2 and later) available in all privilege levels.

Pseudocode Operation

imm16 ← imm4 : imm12
Rd[15:0] ← imm16
Rd[31:16] ← 0

Example

MOVW r0, #16

Encoding

Binary Layout

cond

00110

imm4

imm12

Format Data Proc

Opcode 0x03000000

Extension A32 (Base)

Operands

Rd
Destination general-purpose register
imm16
Value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x03000000	MOV{<c>}{<q>} <Rd>, #<imm16>		A32		cond \| 00110 \| 0 \| 00 \| imm4 \| Rd \| imm12
0xF2400000	MOV{<c>}{<q>} <Rd>, #<imm16>		T32		11110 \| i \| 10 \| 0 \| 100 \| imm4 \| 0 \| imm3 \| Rd \| imm8

Description

Move (immediate) writes an immediate value to the destination register. If the destination register is not the PC, the MOVS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    result = imm32;
    if d == 15 then          // Can only occur for encoding A1
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.N = result<31>;
            PSTATE.Z = IsZeroBit(result);
            PSTATE.C = carry;
            // PSTATE.V unchanged