msr

Move Immediate to Special Register (A32)

MSR <spec_reg>, #<imm>

Writes an immediate to a status register (A32).

Pseudocode Operation

imm_value ← rotate_right(imm8, 2 * rotate)
if spec_reg == CPSR then
  if mask[0] then CPSR[7:0] ← imm_value[7:0]
  if mask[1] then CPSR[15:8] ← imm_value[15:8]
  if mask[2] then CPSR[23:16] ← imm_value[23:16]
  if mask[3] then CPSR[31:24] ← imm_value[31:24]
else if spec_reg == SPSR then
  if mask[0] then SPSR[7:0] ← imm_value[7:0]
  if mask[1] then SPSR[15:8] ← imm_value[15:8]
  if mask[2] then SPSR[23:16] ← imm_value[23:16]
  if mask[3] then SPSR[31:24] ← imm_value[31:24]

Example

MSR nzcv, #16

Encoding

Binary Layout

cond

31:28

00110

27:23

21:20

mask

19:16

imm12

11:0

Format System

Opcode 0x0320F000

Extension A32 (System)

Operands

spec_reg
CPSR/SPSR
imm
Value

Other forms of msr

msr Move to System Register
msr Move to Special Register (Banked)
msr Move Immediate to Special Register (Thumb)
msr Move Register to Special Register (Thumb)
msr Move Register to Status Register

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x0120F200	MSR{<c>}{<q>} <banked_reg>, <Rn>	A32	cond \| 00010 \| R \| 1 \| 0 \| M1 \| 1111 \| 0 \| 0 \| 1 \| M \| 0000 \| Rn
0xF3808020	MSR{<c>}{<q>} <banked_reg>, <Rn>	T32	11110011100 \| R \| Rn \| 10 \| 0 \| 0 \| M1 \| 0 \| 0 \| 1 \| M \| 0 \| 0 \| 0 \| 0
0x0320F000	MSR{<c>}{<q>} <spec_reg>, #<imm>	A32	cond \| 00110 \| R \| 10 \| mask \| 1 \| 1 \| 1 \| 1 \| imm12
0x0120F000	MSR{<c>}{<q>} <spec_reg>, <Rn>	A32	cond \| 00010 \| R \| 1 \| 0 \| mask \| 1111 \| 0 \| 0 \| 0 \| 0 \| 0000 \| Rn
0xF3808000	MSR{<c>}{<q>} <spec_reg>, <Rn>	T32	11110011100 \| R \| Rn \| 10 \| 0 \| 0 \| mask \| 0 \| 0 \| 0 \| 0 \| 0 \| 0 \| 0 \| 0

Description

Move immediate value to Special register moves selected bits of an immediate value to the corresponding bits in the APSR, CPSR, or SPSR_<current_mode>. Because of the Do-Not-Modify nature of its reserved bits, the immediate form of MSR is normally only useful at the Application level for writing to APSR_nzcvq (CPSR_f). If an MSR (immediate) moves selected bits of an immediate value to the CPSR, the PE checks whether the value being written to PSTATE.M is legal. See Illegal changes to PSTATE.M. An MSR (immediate) executed in User mode: An MSR (immediate) executed in System mode is constrained unpredictable if it attempts to update the SPSR. The CPSR.E bit is writable from any mode using an MSR instruction. Arm deprecates using this to change its value.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    if write_spsr then
        if PSTATE.M IN {M32_User,M32_System} then
            UNPREDICTABLE;
        else
            SPSRWriteByInstr(imm32, mask);
    else
        // Attempts to change to an illegal mode will invoke the Illegal Execution state mechanism
        CPSRWriteByInstr(imm32, mask);

msr