adds

Add and Set Flags (Shifted Register)

ADDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Adds shifted register and updates flags.

Pseudocode Operation

shifted_val ← Wm << amount
result ← Wn + shifted_val
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← CarryOut(Wn, shifted_val)
V ← OverflowFrom(Wn, shifted_val)

Example

ADDS w0, w1, w2

Encoding

Binary Layout
0
31
0
30
1
29
01011
28:24
shift
23:22
0
21
Rm
20:16
imm6
15:10
Rn
9:5
Rd
4:0
 
Format Data Processing (Register)
Opcode 0x2B000000
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    First source / base 32-bit integer register
  • Wm
    Second source / offset 32-bit integer register

Related

Other forms of adds

  • adds Add and Set Flags (Extended Register)
  • adds Add and Set Flags (Extended Register 64-bit)
  • adds Add and Set Flags (Immediate)
  • adds Add and Set Flags (Immediate 64-bit)
  • adds Add and Set Flags (Shifted Register 64-bit)

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2B200000 ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}} A64 0 | 0 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd
0xAB200000 ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}} A64 1 | 0 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd
0x31000000 ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>} A64 0 | 0 | 1 | 100010 | sh | imm12 | Rn | Rd
0xB1000000 ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>} A64 1 | 0 | 1 | 100010 | sh | imm12 | Rn | Rd
0x2B000000 ADDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 0 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd
0xAB000000 ADDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 0 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd

Description

Add (shifted register), setting flags, adds a register value and an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.

Operation

bits(datasize) result;
bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);
bits(4) nzcv;


(result, nzcv) = AddWithCarry(operand1, operand2, '0');

PSTATE.<N,Z,C,V> = nzcv;

X[d, datasize] = result;