fmaxv
Floating-Point Maximum Reduction (NEON)
FMAXV <Sd>, <Vn>.<T>
Finds max float in a vector.
Details
Floating-point maximum reduction across vector elements. Scans all floating-point elements in the source vector and writes the maximum value to the destination scalar register. FPSR is updated with cumulative exception flags from all comparisons; condition flags (N, Z, C, V) are unaffected. AArch64-only instruction requiring NEON support.
Pseudocode Operation
elements ← VecReduction(Vn, 'max')
Sd ← FPMaxReduction(elements)
FPSR.IOC ← FPSRAccum from comparisonsExample
FMAXV s0, v1.4s.T
Encoding
Binary Layout
0
Q
0
01110
0
011000
01111
10
Rn
Rd
Operands
-
Sd
Destination 32-bit floating-point register -
Vn
First source SIMD/FP vector register
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0E30F800 | FMAXV <V><d>, <Vn>.<T> | A64 | 0 | Q | 0 | 01110 | 0 | 011000 | 01111 | 10 | Rn | Rd | ||
| 0x6E30F800 | FMAXV S<d>, <Vn>.4S | A64 | 0 | 1 | 1 | 01110 | 0 | 0 | 11000 | 01111 | 10 | Rn | Rd | ||
| 0x65062000 | FMAXV <V><d>, <Pg>, <Zn>.<T> | A64 | 01100101 | size | 000 | 11 | 0 | 001 | Pg | Zn | Vd |
Description
Floating-point Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.
When FPCR.AH is 0, the behavior is as follows:
When FPCR.AH is 1, the behavior is as follows:
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; V[d, esize] = FPReduce(ReduceOp_FMAX, operand, esize, FPCR);