str

Store SIMD&FP Register (Immediate)

STR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>]

Stores a floating-point/SIMD register to memory.

Details

The Store SIMD&FP Register instruction stores a floating-point/SIMD register to memory.

Pseudocode Operation

Memory[address] ← Xn

Example

STR Qt, [x1, #16]

Encoding

Binary Layout
10
111
1
01
00
imm12
Rn
Rt
 
Format Load/Store
Opcode 0xBD000000
Extension Floating Point

Operands

  • Vt
    Transfer SIMD/FP vector register (load/store)
  • Xn
    First source / base 64-bit integer register
  • pimm
    Positive immediate offset

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x3C000400 STR <Bt>, [<Xn|SP>], #<simm> A64 00 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0x7C000400 STR <Ht>, [<Xn|SP>], #<simm> A64 01 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0xBC000400 STR <St>, [<Xn|SP>], #<simm> A64 10 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0xFC000400 STR <Dt>, [<Xn|SP>], #<simm> A64 11 | 111 | 1 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0x3C800400 STR <Qt>, [<Xn|SP>], #<simm> A64 00 | 111 | 1 | 00 | 10 | 0 | imm9 | 01 | Rn | Rt
0x3C000C00 STR <Bt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0x7C000C00 STR <Ht>, [<Xn|SP>, #<simm>]! A64 01 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0xBC000C00 STR <St>, [<Xn|SP>, #<simm>]! A64 10 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0xFC000C00 STR <Dt>, [<Xn|SP>, #<simm>]! A64 11 | 111 | 1 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0x3C800C00 STR <Qt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 1 | 00 | 10 | 0 | imm9 | 11 | Rn | Rt
0x3D000000 STR <Bt>, [<Xn|SP>{, #<pimm>}] A64 00 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt
0x7D000000 STR <Ht>, [<Xn|SP>{, #<pimm>}] A64 01 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt
0xBD000000 STR <St>, [<Xn|SP>{, #<pimm>}] A64 10 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt
0xFD000000 STR <Dt>, [<Xn|SP>{, #<pimm>}] A64 11 | 111 | 1 | 01 | 00 | imm12 | Rn | Rt

Description

Store SIMD&FP register (immediate offset). This instruction stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an immediate offset. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(64) address;
bits(datasize) data;

AccessDescriptor accdesc = CreateAccDescASIMD(memop, FALSE, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

if !postindex then
    address = GenerateAddress(address, offset, accdesc);

case memop of
    when MemOp_STORE
        data = V[t, datasize];
        Mem[address, datasize DIV 8, accdesc] = data;

    when MemOp_LOAD
        data = Mem[address, datasize DIV 8, accdesc];
        V[t, datasize] = data;

if wback then
    if postindex then
        address = GenerateAddress(address, offset, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;