sli

Shift Left and Insert

SLI <Vd>.<T>, <Vn>.<T>, #<shift>

Shifts source left and inserts into destination.

Pseudocode Operation

for i = 0 to elements-1 do
  shifted ← Vn[i] << shift
  Vd[i] ← (Vd[i] & mask) | (shifted & ~mask)
endfor
where mask selects the lower shift bits

Example

SLI v0.4s.T, v1.4s.T, #LSL

Encoding

Binary Layout
0
31
Q
30
1
29
011110
28:23
immh
22:19
immb
18:16
01010
15:11
1
10
Rn
9:5
Rd
4:0
 
Format SIMD Shift Imm
Opcode 0x2F005400
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • shift
    Imm

Related

More in NEON (SIMD)

Reference

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7F405400 SLI D<d>, D<n>, #<shift> A64 01 | 1 | 111110 | immh | immb | 01010 | 1 | Rn | Rd
0x2F005400 SLI <Vd>.<T>, <Vn>.<T>, #<shift> A64 0 | Q | 1 | 011110 | immh | immb | 01010 | 1 | Rn | Rd
0x4500F400 SLI <Zd>.<T>, <Zn>.<T>, #<const> A64 01000101 | tszh | 0 | tszl | imm3 | 11110 | 1 | Zn | Zd

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) operand2 = V[d, datasize];
bits(datasize) result;
bits(esize) mask = LSL(Ones(esize), shift);
bits(esize) shifted;

for e = 0 to elements-1
    shifted = LSL(Elem[operand, e, esize], shift);
    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
V[d, datasize] = result;