vcge

Vector Compare Greater Than or Equal

VCGE<c>.<dt> <Qd>, <Qn>, <Qm>

Compares elements (>=) and sets result mask.

Details

Vector Compare Greater Than or Equal performs signed element-wise comparison on 128-bit SIMD registers. For each element in Qn, if it is greater than or equal to the corresponding element in Qm, the result element in Qd is set to all 1s; otherwise, it is set to all 0s. No condition flags are affected. This is a NEON instruction available in both A32 and T32 states.

Pseudocode Operation

for i = 0 to (128 / element_size) - 1 do
  if Qn[i] >= Qm[i] then
    Qd[i] ← all_ones
  else
    Qd[i] ← all_zeros
  end if
end for

Example

VCGE.dt q0, q1, q2

Encoding

Binary Layout
1111001
U
0
D
size
Vn
Vd
0011
N
0
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2000310
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B10080 VCGE{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0 A32 111100111 | D | 11 | size | 01 | Vd | 0 | F | 001 | 0 | M | 0 | Vm
0xF3B100C0 VCGE{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0 A32 111100111 | D | 11 | size | 01 | Vd | 0 | F | 001 | 1 | M | 0 | Vm
0xFFB10080 VCGE{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0 T32 111111111 | D | 11 | size | 01 | Vd | 0 | F | 001 | 0 | M | 0 | Vm
0xFFB100C0 VCGE{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0 T32 111111111 | D | 11 | size | 01 | Vd | 0 | F | 001 | 1 | M | 0 | Vm
0xF2000310 VCGE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 0 | M | 1 | Vm
0xF2000350 VCGE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | U | 0 | D | size | Vn | Vd | 0011 | N | 1 | M | 1 | Vm
0xF3000E00 VCGE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1110 | N | 0 | M | 0 | Vm
0xF3000E40 VCGE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1110 | N | 1 | M | 0 | Vm
0xEF000310 VCGE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | U | 11110 | D | size | Vn | Vd | 0011 | N | 0 | M | 1 | Vm
0xEF000350 VCGE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | U | 11110 | D | size | Vn | Vd | 0011 | N | 1 | M | 1 | Vm
0xFF000E00 VCGE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | 1 | 11110 | D | 0 | sz | Vn | Vd | 1110 | N | 0 | M | 0 | Vm
0xFF000E40 VCGE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | 1 | 11110 | D | 0 | sz | Vn | Vd | 1110 | N | 1 | M | 0 | Vm

Description

Vector Compare Greater Than or Equal takes each element in a vector, and compares it with the corresponding element of a second vector. If the first is greater than or equal to the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros. The operand vector elements are the same type, and are signed integers, unsigned integers, or floating-point numbers. The result vector elements are fields the same size as the operand vector elements. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Elem[D[n+r],e,esize];  op2 = Elem[D[m+r],e,esize];
            boolean test_passed;
            case vtype of
                when VCGEType_signed    test_passed = (SInt(op1) >= SInt(op2));
                when VCGEType_unsigned  test_passed = (UInt(op1) >= UInt(op2));
                when VCGEType_fp        test_passed = FPCompareGE(op1, op2, StandardFPSCRValue());
            Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);