adc.w

Add with Carry (Wide)

ADC.W <Rd>, <Rn>, <Operand2>

Thumb-2 32-bit add with carry (Access high registers/large constants).

Details

Adds Rn and Operand2 plus the Carry flag value, storing the result in Rd. If S=1, the N, Z, C, V flags are updated based on the result; otherwise flags are unaffected. This is a Thumb-2 32-bit instruction that allows use of high registers (R8–R15) and larger constant operands than 16-bit Thumb ADC.

Pseudocode Operation

result ← Rn + Operand2 + C; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← CarryOut(Rn, Operand2, C); V ← OverflowFrom(Rn, Operand2, C);

Example

ADC.W r0, r1, r2

Encoding

Binary Layout
1110101
1010
0
Rn
0
imm3
Rd
imm2
stype
Rm
 
Format Thumb2 Data Proc
Opcode 0xEB400000
Extension T32 (Thumb2)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Operand2
    Flexible second operand (register or shifted register)

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x02A00000 ADC{<c>}{<q>} {<Rd>,} <Rn>, #<const> A32 cond | 0010 | 101 | 0 | Rn | Rd | imm12
0xF1400000 ADC{<c>}{<q>} {<Rd>,} <Rn>, #<const> T32 11110 | i | 0 | 1010 | 0 | Rn | 0 | imm3 | Rd | imm8
0x00A00060 ADC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX A32 cond | 0000 | 101 | 0 | Rn | Rd | 00000 | 11 | 0 | Rm
0x00A00000 ADC{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} A32 cond | 0000 | 101 | 0 | Rn | Rd | imm5 | stype | 0 | Rm
0x4140 ADC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> T32 010000 | 0101 | Rm | Rdn
0xEB400030 ADC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX T32 1110101 | 1010 | 0 | Rn | 0 | 000 | Rd | 00 | 11 | Rm
0xEB400000 ADC<c>.W {<Rd>,} <Rn>, <Rm> T32 1110101 | 1010 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm
0x00A00010 ADC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> A32 cond | 0000 | 101 | 0 | Rn | Rd | Rs | 0 | stype | 1 | Rm

Description

Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register. If the destination register is not the PC, the ADCS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    shifted = Shift(R[m], shift_t, shift_n, PSTATE.C);
    (result, nzcv) = AddWithCarry(R[n], shifted, PSTATE.C);
    if d == 15 then          // Can only occur for A32 encoding
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.<N,Z,C,V> = nzcv;