sm3partw2

SM3 Part Word 2 (A32)

SM3PARTW2.32 <Qd>, <Qn>, <Qm>

SM3 schedule update part 2.

Details

SM3 Part Word 2 performs the second part of SM3 message schedule update, completing the computation of new message schedule words from previous values. This instruction operates on three 128-bit registers and does not affect condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.

Pseudocode Operation

Qd ← SM3_PARTW2(Qn, Qm)

Example

SM3PARTW2.32 q0, q1, q2

Encoding

Binary Layout
11001110011
Rm
1
1
00
01
Rn
Rd
 
Format Crypto 3-Reg
Opcode 0xCE60C400
Extension Crypto (SM3)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xCE60C400 SM3PARTW2 <Vd>.4S, <Vn>.4S, <Vm>.4S A64 11001110011 | Rm | 1 | 1 | 00 | 01 | Rn | Rd

Description

SM3PARTW2 takes three 128-bit vectors from three source SIMD&FP registers and returns a 128-bit result in the destination SIMD&FP register. The result is obtained by a three-way exclusive-OR of the elements within the input vectors with some fixed rotations, see the Operation pseudocode for more information. This instruction is implemented only when FEAT_SM3 is implemented.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) Vm = V[m, 128];
bits(128) Vn = V[n, 128];
bits(128) Vd = V[d, 128];
bits(128) result;
bits(128) tmp;
bits(32) tmp2;
tmp<127:0> = Vn EOR (ROL(Vm<127:96>, 7):ROL(Vm<95:64>, 7):ROL(Vm<63:32>, 7):ROL(Vm<31:0>, 7));
result<127:0> = Vd<127:0> EOR tmp<127:0>;
tmp2 = ROL(tmp<31:0>, 15);
tmp2 = tmp2 EOR ROL(tmp2, 15) EOR ROL(tmp2, 23);
result<127:96> = result<127:96> EOR tmp2;
V[d, 128] = result;