vpaddl
Vector Pairwise Add Long
VPADDL<c>.<dt> <Qd>, <Qm>
Adds adjacent pairs and produces wide result.
Pseudocode Operation
for i = 0 to (pairs_in_Qm - 1)
Qd[i] ← Qm[2*i] + Qm[2*i+1]Example
VPADDL.dt q0, q2
Encoding
Binary Layout
111100111
31:23
D
22
11
21:20
size
19:18
00
17:16
Vd
15:12
0
11
010
10:8
op
7
0
6
M
5
0
4
Vm
3:0
Operands
-
Qd
Destination 128-bit SIMD register -
Qm
Second source 128-bit SIMD register
Related
More in NEON (SIMD)
Reference
View in Arm A64 ISA Reference ↗
Arm AArch32 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xF3B00200 | VPADDL{<c>}{<q>}.<dt> <Dd>, <Dm> | A32 | 111100111 | D | 11 | size | 00 | Vd | 0 | 010 | op | 0 | M | 0 | Vm | ||
| 0xF3B00240 | VPADDL{<c>}{<q>}.<dt> <Qd>, <Qm> | A32 | 111100111 | D | 11 | size | 00 | Vd | 0 | 010 | op | 1 | M | 0 | Vm | ||
| 0xFFB00200 | VPADDL{<c>}{<q>}.<dt> <Dd>, <Dm> | T32 | 111111111 | D | 11 | size | 00 | Vd | 0 | 010 | op | 0 | M | 0 | Vm | ||
| 0xFFB00240 | VPADDL{<c>}{<q>}.<dt> <Qd>, <Qm> | T32 | 111111111 | D | 11 | size | 00 | Vd | 0 | 010 | op | 1 | M | 0 | Vm |
Description
Vector Pairwise Add Long adds adjacent pairs of elements of two vectors, and places the results in the destination vector. The vectors can be doubleword or quadword. The operand elements can be 8-bit, 16-bit, or 32-bit integers. The result elements are twice the length of the operand elements. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
h = elements DIV 2;
for r = 0 to regs-1
for e = 0 to h-1
op1 = Elem[D[m+r],2*e,esize]; op2 = Elem[D[m+r],2*e+1,esize];
result = Int(op1, unsigned) + Int(op2, unsigned);
Elem[D[d+r],e,2*esize] = result<2*esize-1:0>;