vpaddl

Vector Pairwise Add Long

VPADDL<c>.<dt> <Qd>, <Qm>

Adds adjacent pairs and produces wide result.

Details

Vector Pairwise Add Long adds adjacent pairs of elements from the source register and produces a widened result in the destination register. The data type and element size are specified by the size field; both signed and unsigned variants exist. No condition flags are affected. The destination elements are wider than the source elements to accommodate the pair sums.

Pseudocode Operation

for i = 0 to (pairs_in_Qm - 1)
  Qd[i] ← Qm[2*i] + Qm[2*i+1]

Example

VPADDL.dt q0, q2

Encoding

Binary Layout
111100111
D
11
size
00
Vd
0
010
op
0
M
0
Vm
 
Format NEON 2-Reg
Opcode 0xF3B00200
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B00200 VPADDL{<c>}{<q>}.<dt> <Dd>, <Dm> A32 111100111 | D | 11 | size | 00 | Vd | 0 | 010 | op | 0 | M | 0 | Vm
0xF3B00240 VPADDL{<c>}{<q>}.<dt> <Qd>, <Qm> A32 111100111 | D | 11 | size | 00 | Vd | 0 | 010 | op | 1 | M | 0 | Vm
0xFFB00200 VPADDL{<c>}{<q>}.<dt> <Dd>, <Dm> T32 111111111 | D | 11 | size | 00 | Vd | 0 | 010 | op | 0 | M | 0 | Vm
0xFFB00240 VPADDL{<c>}{<q>}.<dt> <Qd>, <Qm> T32 111111111 | D | 11 | size | 00 | Vd | 0 | 010 | op | 1 | M | 0 | Vm

Description

Vector Pairwise Add Long adds adjacent pairs of elements of two vectors, and places the results in the destination vector. The vectors can be doubleword or quadword. The operand elements can be 8-bit, 16-bit, or 32-bit integers. The result elements are twice the length of the operand elements. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    h = elements DIV 2;

    for r = 0 to regs-1
        for e = 0 to h-1
            op1 = Elem[D[m+r],2*e,esize];  op2 = Elem[D[m+r],2*e+1,esize];
            result = Int(op1, unsigned) + Int(op2, unsigned);
            Elem[D[d+r],e,2*esize] = result<2*esize-1:0>;