adc

Add with Carry (A32)

ADC{S}<c> <Rd>, <Rn>, <Rm> {, <shift>}

Adds two 32-bit values and the Carry flag.

Details

Adds two 32-bit values from Rn and Rm along with the Carry flag (C) and stores the result in Rd. If the S bit is set, the condition flags are updated: N and Z reflect the result, C is set on unsigned overflow, V is set on signed overflow. The shift operand is optional and applies a shift to Rm before the addition. This is an A32 instruction with conditional execution.

Pseudocode Operation

shifted_Rm ← ApplyShift(Rm, shift)
result ← Rn + shifted_Rm + C
Rd ← result
if S then
  N ← result[31]
  Z ← (result == 0)
  C ← CarryOut(Rn + shifted_Rm + C)
  V ← OverflowFrom(Rn + shifted_Rm + C)

Example

ADC r0, r1, r2

Encoding

Binary Layout
cond
0000
101
0
Rn
Rd
imm5
stype
0
Rm
 
Format Data Proc
Opcode 0x00A00000
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x02A00000 ADC{<c>}{<q>} {<Rd>,} <Rn>, #<const> A32 cond | 0010 | 101 | 0 | Rn | Rd | imm12
0xF1400000 ADC{<c>}{<q>} {<Rd>,} <Rn>, #<const> T32 11110 | i | 0 | 1010 | 0 | Rn | 0 | imm3 | Rd | imm8
0x00A00060 ADC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX A32 cond | 0000 | 101 | 0 | Rn | Rd | 00000 | 11 | 0 | Rm
0x00A00000 ADC{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} A32 cond | 0000 | 101 | 0 | Rn | Rd | imm5 | stype | 0 | Rm
0x4140 ADC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> T32 010000 | 0101 | Rm | Rdn
0xEB400030 ADC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX T32 1110101 | 1010 | 0 | Rn | 0 | 000 | Rd | 00 | 11 | Rm
0xEB400000 ADC<c>.W {<Rd>,} <Rn>, <Rm> T32 1110101 | 1010 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm
0x00A00010 ADC{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> A32 cond | 0000 | 101 | 0 | Rn | Rd | Rs | 0 | stype | 1 | Rm

Description

Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register. If the destination register is not the PC, the ADCS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    shifted = Shift(R[m], shift_t, shift_n, PSTATE.C);
    (result, nzcv) = AddWithCarry(R[n], shifted, PSTATE.C);
    if d == 15 then          // Can only occur for A32 encoding
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.<N,Z,C,V> = nzcv;