and

Bitwise AND (Shifted Register 64-bit)

AND <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

Bitwise AND with shifted register (64-bit).

Details

The Bitwise AND instruction bitwise AND with shifted register (64-bit).

Pseudocode Operation

Xd ← Xn AND Xm

Example

AND x0, x1, x2

Encoding

Binary Layout
10001010
00
Rm
imm6
Rn
Rd
 
Format Logical (Register)
Opcode 0x8A000000
Extension Base

Operands

  • Xd
    Destination 64-bit integer register
  • Xn
    First source / base 64-bit integer register
  • Xm
    Second source / offset 64-bit integer register