vnmul

Vector Negated Multiply (VFP)

VNMUL<c>.F32 <Sd>, <Sn>, <Sm>

Sd = -(Sn * Sm).

Pseudocode Operation

product ← FP_Multiply(Sn, Sm)
Sd ← FP_Negate(product)
FPSCR ← updated with floating-point exception flags

Example

VNMUL.F32 s0, s1, s2

Encoding

Binary Layout

cond

31:28

1110

27:24

0

23

D

22

10

21:20

Vn

19:16

Vd

15:12

10

11:10

10

9:8

N

7

1

6

M

5

0

4

Vm

3:0

 

Format VFP Arith

Opcode 0x0E200A40

Extension VFP (Float)

Operands

• Sd
  Destination 32-bit floating-point register
• Sn
  First source 32-bit floating-point register
• Sm
  Second source 32-bit floating-point register

Related

More in VFP (Float)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0E200940	VNMUL{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm>		A32		cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 01 | N | 1 | M | 0 | Vm
0x0E200A40	VNMUL{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>		A32		cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm
0x0E200B40	VNMUL{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>		A32		cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm
0xEE200940	VNMUL{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm>		T32		11101110 | 0 | D | 10 | Vn | Vd | 10 | 01 | N | 1 | M | 0 | Vm
0xEE200A40	VNMUL{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>		T32		11101110 | 0 | D | 10 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm
0xEE200B40	VNMUL{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>		T32		11101110 | 0 | D | 10 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm

Description

Vector Negate Multiply multiplies together two floating-point register values, and writes the negation of the result to the destination register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    case esize of
        when 16
            product16 = FPMul(S[n]<15:0>, S[m]<15:0>, FPSCR[]);
            case vtype of
                when VFPNegMul_VNMLA  S[d] = (Zeros(16) : FPAdd(FPNeg(S[d]<15:0>),
                                                                FPNeg(product16), FPSCR[]));
                when VFPNegMul_VNMLS  S[d] = (Zeros(16) : FPAdd(FPNeg(S[d]<15:0>),
                                                                product16, FPSCR[]));
                when VFPNegMul_VNMUL  S[d] =  Zeros(16) : FPNeg(product16);
        when 32
            product32 = FPMul(S[n], S[m], FPSCR[]);
            case vtype of
                when VFPNegMul_VNMLA  S[d] = FPAdd(FPNeg(S[d]), FPNeg(product32), FPSCR[]);
                when VFPNegMul_VNMLS  S[d] = FPAdd(FPNeg(S[d]), product32, FPSCR[]);
                when VFPNegMul_VNMUL  S[d] = FPNeg(product32);
        when 64
            product64 = FPMul(D[n], D[m], FPSCR[]);
            case vtype of
                when VFPNegMul_VNMLA  D[d] = FPAdd(FPNeg(D[d]), FPNeg(product64), FPSCR[]);
                when VFPNegMul_VNMLS  D[d] = FPAdd(FPNeg(D[d]), product64, FPSCR[]);
                when VFPNegMul_VNMUL  D[d] = FPNeg(product64);