sha256h

SHA256 Hash Part 1 (A32)

SHA256H.32 <Qd>, <Qn>, <Qm>

SHA256 hash update (part 1).

Details

SHA256 Hash Part 1 performs the first half of a SHA256 hash update operation on 128-bit NEON registers, processing the W array intermediate values. Qd receives updated hash state W[t] and W[t+1]; Qn provides the previous hash state; Qm provides the input data block words. This A32 Crypto extension instruction does not update condition flags and requires NEON support.

Pseudocode Operation

hash_state ← Qd;
w_data ← Qn;
data_words ← Qm;
temp ← SHA256_CH(hash_state.word[1], hash_state.word[2], hash_state.word[3]);
temp ← temp + SHA256_SUM1(hash_state.word[1]);
temp ← temp + data_words;
Qd.word[0] ← Qd.word[0] + temp;
Qd.word[1] ← hash_state.word[0];

Example

SHA256H.32 q0, q1, q2

Encoding

Binary Layout
11110011
0
0
0
Vn
Vd
1100
N
Q
M
0
Vm
 
Format Crypto 3-Reg
Opcode 0xF3000C00
Extension Crypto

Operands

  • Qd
    State
  • Qn
    Hash
  • Qm
    Data

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5E004000 SHA256H <Qd>, <Qn>, <Vm>.4S A64 01011110 | 00 | 0 | Rm | 010 | 0 | 00 | Rn | Rd

Description

SHA256 hash update (part 1).

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) result;
result = SHA256hash(V[d, 128], V[n, 128], V[m, 128], TRUE);
V[d, 128] = result;