vusmmla

Vector Unsigned-Signed Matrix Multiply (A32)

VUSMMLA<c>.S8 <Qd>, <Qn>, <Qm>

Matrix multiply-accumulate (Unsigned x Signed Int8).

Details

Multiplies two 128-bit SIMD registers containing unsigned 8-bit integers from Qn and signed 8-bit integers from Qm in 4×4 matrix format and accumulates the result into the destination register as signed 32-bit integers. Processes four 4×4 matrices, each producing four 32-bit signed results. Condition flags are unaffected. This instruction requires the NEON MatMul extension and executes in A32 (ARM) instruction set only.

Pseudocode Operation

for i = 0 to 3 do
  // Extract 4x4 U8 matrix from Qn
  for r = 0 to 3 do
    for c = 0 to 3 do
      matrix_a[r][c] = ZeroExtend(Qn[(i*16 + r*4 + c)*8 + 0:7])
  // Extract 4x4 S8 matrix from Qm
  for r = 0 to 3 do
    for c = 0 to 3 do
      matrix_b[r][c] = SignExtend(Qm[(i*16 + r*4 + c)*8 + 0:7])
  // Multiply and accumulate
  for r = 0 to 3 do
    result = Qd[(i*4 + r)*32 + 0:31]
    for k = 0 to 3 do
      result = result + matrix_a[r][k] * matrix_b[k][r]
    Qd[(i*4 + r)*32 + 0:31] = result

Example

VUSMMLA.S8 q0, q1, q2

Encoding

Binary Layout
1111110
0
1
D
10
Vn
Vd
1
1
0
0
N
1
M
0
Vm
 
Format NEON MatMul
Opcode 0xFCA00C40
Extension NEON (MatMul)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    Unsigned
  • Qm
    Signed

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xFCA00C40 VUSMMLA{<q>}.S8 <Qd>, <Qn>, <Qm> A32 1111110 | 0 | 1 | D | 10 | Vn | Vd | 1 | 1 | 0 | 0 | N | 1 | M | 0 | Vm

Description

The widening integer matrix multiply-accumulate instruction multiplies the 2x8 matrix of unsigned 8-bit integer values held in the first source vector by the 8x2 matrix of signed 8-bit integer values in the second source vector. The resulting 2x2 32-bit integer matrix product is destructively added to the 32-bit integer matrix accumulator held in the destination vector. This is equivalent to performing an 8-way dot product per destination element. From Armv8.2, this is an optional instruction. ID_ISAR6.I8MM indicates whether this instruction is supported in the T32 and A32 instruction sets.

Operation

CheckAdvSIMDEnabled();
bits(128) operand1 = Q[n>>1];
bits(128) operand2 = Q[m>>1];
bits(128) addend   = Q[d>>1];

Q[d>>1] = MatMulAdd(addend, operand1, operand2, op1_unsigned, op2_unsigned);