fcvtn

Floating-Point Convert Narrow (Single to Half)

FCVTN <Vd>.4H, <Vn>.4S

Converts Single-precision to Half-precision (Bottom).

Details

Converts the lower 4 single-precision (FP32) floating-point values from the source vector to half-precision (FP16) and writes them to the lower half of the destination vector. Requires FEAT_FP16. Condition flags are not affected; may raise floating-point exceptions during conversion.

Pseudocode Operation

for i = 0 to 3
  Vd.H[i] ← FP32_to_FP16(Vn.S[i])
endfor

Example

FCVTN v0.4s.4H, v1.4s.4S

Encoding

Binary Layout
0
Q
0
011100
sz
10000
10110
10
Rn
Rd
 
Format NEON FP16
Opcode 0x0E216800
Extension FEAT_FP16 (NEON)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E216800 FCVTN{2} <Vd>.<Tb>, <Vn>.<Ta> A64 0 | Q | 0 | 011100 | sz | 10000 | 10110 | 10 | Rn | Rd
0x0E40F400 FCVTN <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> A64 0 | Q | 0 | 01110 | 01 | 0 | Rm | 1 | 1110 | 1 | Rn | Rd
0x0E00F400 FCVTN{2} <Vd>.<Ta>, <Vn>.4S, <Vm>.4S A64 0 | Q | 0 | 01110 | 00 | 0 | Rm | 1 | 1110 | 1 | Rn | Rd
0x650A3000 FCVTN <Zd>.B, { <Zn1>.H-<Zn2>.H } A64 01100101000010100011 | 0 | 0 | Zn | 0 | Zd
0xC134E020 FCVTN <Zd>.B, { <Zn1>.S-<Zn4>.S } A64 1100000100110100111000 | Zn | 0 | 1 | Zd
0xC120E020 FCVTN <Zd>.H, { <Zn1>.S-<Zn2>.S } A64 110000010 | 0 | 100000111000 | Zn | 1 | Zd

Description

Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR. FCVTN writes the vector to the lower half of the destination register and clears the upper half. FCVTN2 writes the vector to the upper half of the destination register without affecting the other bits of the register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand = V[n, 2*datasize];
bits(datasize) result;

for e = 0 to elements-1
    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR, esize);

Vpart[d, part, datasize] = result;