sdiv

Signed Divide (A32)

SDIV<c> <Rd>, <Rn>, <Rm>

Signed integer division.

Details

Signed Divide performs signed integer division of Rn (dividend) by Rm (divisor), storing the quotient in Rd. Division by zero does not raise an exception; the result is architecturally unpredictable. No condition flags are modified by this instruction. SDIV is available only in A32 with the Divide extension (ARMv7-R, ARMv7-A with hardware divide).

Pseudocode Operation

if Rm == 0 then
  Rd ← UNPREDICTABLE;
else
  Rd ← SignedDivide(Rn, Rm);
endif;

Example

SDIV r0, r1, r2

Encoding

Binary Layout
cond
01110
001
Rd
1111
Rm
000
1
Rn
 
Format Data Proc
Opcode 0x0710F010
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    Dividend
  • Rm
    Divisor

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0710F010 SDIV{<c>}{<q>} {<Rd>,} <Rn>, <Rm> A32 cond | 01110 | 001 | Rd | 1111 | Rm | 000 | 1 | Rn
0xFB90F0F0 SDIV{<c>}{<q>} {<Rd>,} <Rn>, <Rm> T32 111110111 | 001 | Rn | 1111 | Rd | 1111 | Rm

Description

Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    integer result;
    if SInt(R[m]) == 0 then
        result = 0;
    else
        result = RoundTowardsZero(Real(SInt(R[n])) / Real(SInt(R[m])));
    R[d] = result<31:0>;