ldrh

Load Register Halfword (A32)

LDRH<c> <Rt>, [<Rn>, #+/-<imm>]

Loads a halfword (Zero extended).

Pseudocode Operation

offset ← ZeroExtend(imm4H:imm4L) << 1;
if U == 1 then address ← Rn + offset else address ← Rn - offset;
if P == 1 then address ← address else address ← Rn;
Rt ← ZeroExtend(MemRead(address, 2));
if W == 1 then Rn ← address;

Example

LDRH r3, [r1, #+/-#16]

Encoding

Binary Layout
cond
31:28
000
27:25
1
24
U
23
1
22
1
21
1
20
Rn
19:16
Rt
15:12
imm4H
11:8
1
7
01
6:5
1
4
imm4L
3:0
 
Format Load/Store
Opcode 0x017000B0
Extension A32 (Base)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Related

Other forms of ldrh

  • ldrh Load Register Halfword (Immediate)
  • ldrh Load Register Halfword (Register)

More in A32 (Base)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x015000B0 LDRH{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}] A32 cond | 000 | 1 | U | 1 | 0 | 1 | Rn | Rt | imm4H | 1 | 01 | 1 | imm4L
0x005000B0 LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> A32 cond | 000 | 0 | U | 1 | 0 | 1 | Rn | Rt | imm4H | 1 | 01 | 1 | imm4L
0x017000B0 LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! A32 cond | 000 | 1 | U | 1 | 1 | 1 | Rn | Rt | imm4H | 1 | 01 | 1 | imm4L
0x8800 LDRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] T32 1000 | 1 | imm5 | Rn | Rt
0xF8B00000 LDRH{<c>}.W <Rt>, [<Rn> {, #{+}<imm>}] T32 111110001 | 01 | 1 | Rn | Rt | imm12
0xF8300C00 LDRH{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}] T32 111110000 | 01 | 1 | Rn | Rt | 1 | 1 | 0 | 0 | imm8
0xF8300900 LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> T32 111110000 | 01 | 1 | Rn | Rt | 1 | 0 | U | 1 | imm8
0xF8300D00 LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! T32 111110000 | 01 | 1 | Rn | Rt | 1 | 1 | U | 1 | imm8
0x005F00B0 LDRH{<c>}{<q>} <Rt>, <label> A32 cond | 000 | P | U | 1 | W | 1 | 1111 | Rt | imm4H | 1 | 01 | 1 | imm4L
0xF83F0000 LDRH{<c>}{<q>} <Rt>, <label> T32 11111000 | U | 01 | 1 | 1111 | Rt | imm12
0x011000B0 LDRH{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>] A32 cond | 000 | 1 | U | 0 | 0 | 1 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 01 | 1 | Rm
0x001000B0 LDRH{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm> A32 cond | 000 | 0 | U | 0 | 0 | 1 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 01 | 1 | Rm
0x013000B0 LDRH{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>]! A32 cond | 000 | 1 | U | 0 | 1 | 1 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 01 | 1 | Rm
0x5A00 LDRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] T32 0101 | 1 | 0 | 1 | Rm | Rn | Rt

Description

Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

Operation

if CurrentInstrSet() == InstrSet_A32 then
    if ConditionPassed() then
        EncodingSpecificOperations();
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        data = MemU[address,2];
        if wback then R[n] = offset_addr;
        R[t] = ZeroExtend(data, 32);
else
    if ConditionPassed() then
        EncodingSpecificOperations();
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        data = MemU[address,2];
        if wback then R[n] = offset_addr;
        R[t] = ZeroExtend(data, 32);