uqxtn

Unsigned Saturating Extract Narrow

UQXTN <Vd>.<Tb>, <Vn>.<Ta>

Reads wide unsigned elements, saturates, and narrows.

Details

Extracts each unsigned element from a wide source vector, saturates to the range of the narrower unsigned destination type, and stores the result. Sets the FPSR.QC flag if saturation occurs. This is an AArch64 NEON instruction; no general-purpose flags are modified.

Pseudocode Operation

for i = 0 to elements-1 do
  temp ← Vn[i]
  if temp > max_value_dest then
    Vd[i] ← max_value_dest
    FPSR.QC ← 1
  else
    Vd[i] ← temp
  endif
endfor

Example

UQXTN v0.4s.Tb, v1.4s.Ta

Encoding

Binary Layout
0
Q
1
01110
size
10000
10100
10
Rn
Rd
 
Format SIMD Shift Imm
Opcode 0x2E214800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7E214800 UQXTN <Vb><d>, <Va><n> A64 01 | 1 | 11110 | size | 10000 | 10100 | 10 | Rn | Rd
0x2E214800 UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta> A64 0 | Q | 1 | 01110 | size | 10000 | 10100 | 10 | Rn | Rd

Description

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. If saturation occurs, the cumulative saturation bit FPSR.QC is set. The UQXTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the UQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand = V[n, 2*datasize];
bits(datasize) result;
bits(2*esize) element;
boolean sat;

for e = 0 to elements-1
    element = Elem[operand, e, 2*esize];
    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
    if sat then FPSR.QC = '1';

Vpart[d, part, datasize] = result;