uxtb16

Unsigned Extend Byte 16 (A32)

UXTB16<c> <Rd>, <Rm> {, <rotation>}

Zero-extends two bytes to two halfwords.

Pseudocode Operation

rotated ← ROR(Rm, rotation); Rd<15:0> ← ZeroExtend(rotated<7:0>, 16); Rd<31:16> ← ZeroExtend(rotated<15:8>, 16);

Example

UXTB16 r0, r2

Encoding

Binary Layout

cond

31:28

01101

27:23

1

22

00

21:20

1111

19:16

Rd

15:12

rotate

11:10

0

9

0

8

0111

7:4

Rm

3:0

 

Format Data Proc

Opcode 0x06CF0070

Extension A32 (DSP)

Operands

• Rd
  Destination general-purpose register
• Rm
  Second source / offset general-purpose register

Related

More in A32 (DSP)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x06CF0070	UXTB16{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>}		A32		cond | 01101 | 1 | 00 | 1111 | Rd | rotate | 0 | 0 | 0111 | Rm
0xFA3FF080	UXTB16{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>}		T32		111110100 | 01 | 1 | 1111 | 1111 | Rd | 1 | 0 | rotate | Rm

Description

Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d]<15:0>  = ZeroExtend(rotated<7:0>, 16);
    R[d]<31:16> = ZeroExtend(rotated<23:16>, 16);