zip1

Vector Zip 1 (Interleave)

ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Interleaves the lower halves of two vectors.

Details

The Vector Zip 1 instruction interleaves the lower halves of two vectors.

Pseudocode Operation

// Interleaves the lower halves of two vectors

Example

ZIP1 v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
001110
size
0
Rm
0011
10
Rn
Rd
 
Format SIMD Permute
Opcode 0x0E003800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register