zip1

Vector Zip 1 (Interleave)

ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Interleaves the lower halves of two vectors.

Details

Interleaves the lower halves of two vectors by taking alternate elements from Vn and Vm and writing them to Vd. This is a pure data movement operation with no flag updates. Execution is restricted to AArch64 with NEON support (ARMv8.0+) and does not require elevated privilege.

Pseudocode Operation

bits(128) result;
for e = 0 to (esize/8)-1
  result[e*16 +: 8] ← Vn[e*16 +: 8];
  result[e*16 + 8 +: 8] ← Vm[e*16 +: 8];
if Q == 0 then
  Vd ← result[0 +: 64];
else
  Vd ← result;

Example

ZIP1 v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
001110
size
0
Rm
0
0
1110
Rn
Rd
 
Format SIMD Permute
Opcode 0x0E003800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E003800 ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 001110 | size | 0 | Rm | 0 | 0 | 1110 | Rn | Rd
0x05204000 ZIP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T> A64 00000101 | size | 10 | Pm | 010 | 0 | 0 | 0 | 0 | Pn | 0 | Pd
0x05206000 ZIP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 00000101 | size | 1 | Zm | 011 | 00 | 0 | Zn | Zd
0x05A00000 ZIP1 <Zd>.Q, <Zn>.Q, <Zm>.Q A64 00000101101 | Zm | 000 | 0 | 0 | 0 | Zn | Zd

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;

integer base = part * pairs;

for p = 0 to pairs-1
    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];

V[d, datasize] = result;