fcvtzs

Vector Floating-Point Convert to Signed Integer

FCVTZS <Vd>.<T>, <Vn>.<T> {, #<fbits>}

Converts floats to signed integers (Truncate).

Details

Converts a vector of floating-point elements to a vector of signed integer elements by truncating toward zero, with optional fixed-point scaling (fbits). Executes in AArch64 with NEON support; condition flags are not affected. Overflow wraps to the minimum/maximum signed integer value for the element size.

Pseudocode Operation

for i = 0 to num_elements-1 do
  if fbits specified then
    scaled ← Vn[i] * 2^fbits
  else
    scaled ← Vn[i]
  Vd[i] ← ConvertToSignedInteger(scaled, rounding_mode=toward_zero)

Example

FCVTZS v0.4s.T, v1.4s.T

Encoding

Binary Layout
0
Q
0
011110
immh
immb
11111
1
Rn
Rd
 
Format SIMD Two Register
Opcode 0x0F00FC00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5F00FC00 FCVTZS <V><d>, <V><n>, #<fbits> A64 01 | 0 | 111110 | immh | immb | 11111 | 1 | Rn | Rd
0x0F00FC00 FCVTZS <Vd>.<T>, <Vn>.<T>, #<fbits> A64 0 | Q | 0 | 011110 | immh | immb | 11111 | 1 | Rn | Rd
0x5EF9B800 FCVTZS <Hd>, <Hn> A64 01 | 0 | 11110 | 1 | 1111001101 | 1 | 10 | Rn | Rd
0x5EA1B800 FCVTZS <V><d>, <V><n> A64 01 | 0 | 11110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd
0x0EF9B800 FCVTZS <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 1 | 1111001101 | 1 | 10 | Rn | Rd
0x0EA1B800 FCVTZS <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd
0x1ED80000 FCVTZS <Wd>, <Hn>, #<fbits> A64 0 | 0 | 0 | 11110 | 11 | 0 | 11 | 000 | scale | Rn | Rd
0x9ED80000 FCVTZS <Xd>, <Hn>, #<fbits> A64 1 | 0 | 0 | 11110 | 11 | 0 | 11 | 000 | scale | Rn | Rd
0x1E180000 FCVTZS <Wd>, <Sn>, #<fbits> A64 0 | 0 | 0 | 11110 | 00 | 0 | 11 | 000 | scale | Rn | Rd
0x9E180000 FCVTZS <Xd>, <Sn>, #<fbits> A64 1 | 0 | 0 | 11110 | 00 | 0 | 11 | 000 | scale | Rn | Rd
0x1E580000 FCVTZS <Wd>, <Dn>, #<fbits> A64 0 | 0 | 0 | 11110 | 01 | 0 | 11 | 000 | scale | Rn | Rd
0x9E580000 FCVTZS <Xd>, <Dn>, #<fbits> A64 1 | 0 | 0 | 11110 | 01 | 0 | 11 | 000 | scale | Rn | Rd
0x1EF80000 FCVTZS <Wd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 1 | 11 | 000 | 000000 | Rn | Rd
0x9EF80000 FCVTZS <Xd>, <Hn> A64 1 | 0 | 0 | 11110 | 11 | 1 | 11 | 000 | 000000 | Rn | Rd

Description

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from floating-point to fixed-point signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];

bits(esize) element;
boolean merge = elements == 1 && IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else Zeros(128);
for e = 0 to elements-1
    element = Elem[operand, e, esize];
    Elem[result, e, esize] = FPToFixed(element, fracbits, unsigned, FPCR, rounding, esize);

V[d, 128] = result;