vsqrt

Vector Square Root (Double)

VSQRT<c>.F64 <Dd>, <Dm>

Square root of double-precision register.

Details

Computes the square root of a double-precision floating-point value and stores the result in the destination register. This is a unary VFP operation that performs IEEE 754 compliant square-root computation; if the source is negative (excluding -0), the result is NaN. FPSCR exception flags may be set based on input and result. Requires VFP extension and executes only in A32 instruction set.

Pseudocode Operation

Dd ← sqrt(Dm)
FPSCR.IOC ← 1 if Dm < 0.0 and Dm ≠ -0.0 (invalid operation)
FPSCR.UFC ← 1 if result is subnormal (underflow)
FPSCR.OFC ← 1 if result overflows
FPSCR.IXC ← 1 if result is inexact

Example

VSQRT.F64 d0, d2

Encoding

Binary Layout
cond
11101
D
11
0
001
Vd
10
11
1
1
M
0
Vm
 
Format VFP Unary
Opcode 0x0EB10BC0
Extension VFP (Float)

Operands

  • Dd
    Destination 64-bit SIMD/FP register
  • Dm
    Second source 64-bit SIMD/FP register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EB109C0 VSQRT{<c>}{<q>}.F16 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm
0x0EB10AC0 VSQRT{<c>}{<q>}.F32 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm
0x0EB10BC0 VSQRT{<c>}{<q>}.F64 <Dd>, <Dm> A32 cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm
0xEEB109C0 VSQRT{<c>}{<q>}.F16 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 001 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm
0xEEB10AC0 VSQRT{<c>}{<q>}.F32 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 001 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm
0xEEB10BC0 VSQRT{<c>}{<q>}.F64 <Dd>, <Dm> T32 111011101 | D | 11 | 0 | 001 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm

Description

Square Root calculates the square root of the value in a floating-point register and writes the result to another floating-point register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    case esize of
        when 16 S[d] = Zeros(16) : FPSqrt(S[m]<15:0>, FPSCR[]);
        when 32 S[d] = FPSqrt(S[m], FPSCR[]);
        when 64 D[d] = FPSqrt(D[m], FPSCR[]);