strexb

Store Register Exclusive Byte (Thumb)

STREXB <Rd>, <Rt>, [<Rn>]

Stores byte exclusively (Thumb).

Details

Attempts to store the low byte from Rt to memory at the address in Rn only if the exclusive monitor is open; writes 0 to Rd if successful, or 1 if the store fails. No condition flags are modified. Execution in Thumb-2 state only; used for atomic byte-sized operations.

Pseudocode Operation

address ← Rn
if ExclusiveMonitor[address] then
  [address] ← Rt[7:0]
  Rd ← 0
  ClearExclusiveMonitor()
else
  Rd ← 1

Example

STREXB r0, r3, [r1]

Encoding

Binary Layout
11101000110
0
Rn
Rt
1111
01
00
Rd
 
Format Thumb Store Excl
Opcode 0xE8C00F40
Extension A32 (Atomic)

Operands

  • Rd
    Status
  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01C00F90 STREXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] A32 cond | 00011 | 10 | 0 | Rn | Rd | 1 | 1 | 1 | 1 | 1001 | Rt
0xE8C00F40 STREXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] T32 11101000110 | 0 | Rn | Rt | 1111 | 01 | 00 | Rd

Description

Store Register Exclusive Byte derives an address from a base register value, stores a byte from a register to the derived address if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    if AArch32.ExclusiveMonitorsPass(address,1) then
        MemA[address,1] = R[t]<7:0>;
        R[d] = ZeroExtend('0', 32);
    else
        R[d] = ZeroExtend('1', 32);