bit

Bitwise Insert if True

BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Inserts bits from Vn into Vd where Vm (mask) is 1.

Details

Performs a bitwise insert-if-true operation: Vd ← (Vd & ~Vm) | (Vn & Vm). Bits from Vn are inserted into Vd where the corresponding bit in Vm is 1; Vd bits are retained where Vm is 0. No condition flags are affected. Executes in AArch64 state with NEON extension on both 64-bit (Q=0) and 128-bit (Q=1) vectors.

Pseudocode Operation

for i = 0 to (datasize / 8) - 1
  Vd[i*8 +: 8] ← (Vd[i*8 +: 8] & ~Vm[i*8 +: 8]) | (Vn[i*8 +: 8] & Vm[i*8 +: 8])

Example

BIT v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
1
01110
10
1
Rm
00011
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x2EA01C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Mask

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2EA01C00 BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | 10 | 1 | Rm | 00011 | 1 | Rn | Rd

Description

Bitwise Insert if True. This instruction inserts each bit from the first source SIMD&FP register into the SIMD&FP destination register if the corresponding bit of the second source SIMD&FP register is 1, otherwise leaves the bit in the destination register unchanged. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1;
bits(datasize) operand3;
bits(datasize) operand4 = V[n, datasize];

operand1 = V[d, datasize];
operand3 = V[m, datasize];
V[d, datasize] = operand1 EOR ((operand1 EOR operand4) AND operand3);