vldr

Vector Load Register (VFP)

VLDR<c> <Sd>, [<Rn>, #+/-<imm>]

Loads a floating-point register from memory.

Details

Loads a single-precision floating-point value from memory into a VFP register using a PC-relative or register-relative address with an optional offset. The memory access uses the address [Rn ± (imm8 << 2)]. Executed in A32/T32 with VFP extension; no condition flags are affected.

Pseudocode Operation

offset ← ZeroExtend(imm8) << 2
if U == 1 then
  address ← Rn + offset
else
  address ← Rn - offset
Sd ← [address]

Example

VLDR s0, [r1, #+/-#16]

Encoding

Binary Layout
cond
110
1
U
D
0
1
Rn
Vd
10
10
imm8
 
Format VFP Load
Opcode 0x0D100A00
Extension VFP (Float)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Rn
    First source / base general-purpose register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0D100900 VLDR{<c>}{<q>}.16 <Sd>, [<Rn> {, #{+/-}<imm>}] A32 cond | 110 | 1 | U | D | 0 | 1 | Rn | Vd | 10 | 01 | imm8
0x0D100A00 VLDR{<c>}{<q>}{.32} <Sd>, [<Rn> {, #{+/-}<imm>}] A32 cond | 110 | 1 | U | D | 0 | 1 | Rn | Vd | 10 | 10 | imm8
0x0D100B00 VLDR{<c>}{<q>}{.64} <Dd>, [<Rn> {, #{+/-}<imm>}] A32 cond | 110 | 1 | U | D | 0 | 1 | Rn | Vd | 10 | 11 | imm8
0xED100900 VLDR{<c>}{<q>}.16 <Sd>, [<Rn> {, #{+/-}<imm>}] T32 1110110 | 1 | U | D | 0 | 1 | Rn | Vd | 10 | 01 | imm8
0xED100A00 VLDR{<c>}{<q>}{.32} <Sd>, [<Rn> {, #{+/-}<imm>}] T32 1110110 | 1 | U | D | 0 | 1 | Rn | Vd | 10 | 10 | imm8
0xED100B00 VLDR{<c>}{<q>}{.64} <Dd>, [<Rn> {, #{+/-}<imm>}] T32 1110110 | 1 | U | D | 0 | 1 | Rn | Vd | 10 | 11 | imm8
0x0D1F0900 VLDR{<c>}{<q>}.16 <Sd>, <label> A32 cond | 110 | 1 | U | D | 0 | 1 | 1111 | Vd | 10 | 01 | imm8
0x0D1F0A00 VLDR{<c>}{<q>}{.32} <Sd>, <label> A32 cond | 110 | 1 | U | D | 0 | 1 | 1111 | Vd | 10 | 10 | imm8
0x0D1F0B00 VLDR{<c>}{<q>}{.64} <Dd>, <label> A32 cond | 110 | 1 | U | D | 0 | 1 | 1111 | Vd | 10 | 11 | imm8
0xED1F0900 VLDR{<c>}{<q>}.16 <Sd>, <label> T32 1110110 | 1 | U | D | 0 | 1 | 1111 | Vd | 10 | 01 | imm8
0xED1F0A00 VLDR{<c>}{<q>}{.32} <Sd>, <label> T32 1110110 | 1 | U | D | 0 | 1 | 1111 | Vd | 10 | 10 | imm8
0xED1F0B00 VLDR{<c>}{<q>}{.64} <Dd>, <label> T32 1110110 | 1 | U | D | 0 | 1 | 1111 | Vd | 10 | 11 | imm8

Description

Load SIMD&FP register (immediate) loads a single register from the Advanced SIMD and floating-point register file, using an address from a general-purpose register, with an optional offset. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    CheckVFPEnabled(TRUE);
    base = if n == 15 then Align(PC,4) else R[n];
    address = if add then (base + imm32) else (base - imm32);
    case esize of
        when 16
            S[d] = Zeros(16) : MemA[address,2];
        when 32
            S[d] = MemA[address,4];
        when 64
            word1 = MemA[address,4];
            word2 = MemA[address+4,4];
            // Combine the word-aligned words in the correct order for current endianness.
            D[d] = if BigEndian(AccessType_ASIMD) then word1:word2 else word2:word1;