vldr

Vector Load Register (VFP)

VLDR<c> <Sd>, [<Rn>, #+/-<imm>]

Loads a floating-point register from memory.

Details

The Vector Load Register instruction loads a floating-point register from memory.

Pseudocode Operation

// Loads a floating-point register from memory

Example

VLDR s0, [r1, #+/-#16]

Encoding

Binary Layout
cond
1101
U
001
Rn
Vd
1010
imm8
 
Format VFP Load
Opcode 0x0D100A00
Extension VFP (Float)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Rn
    First source / base general-purpose register
  • imm
    Signed immediate value