ptrue

SVE Initialize Predicate to True

PTRUE <Pd>.<T> {, <pattern>}

Sets elements of the predicate register to true (all active).

Pseudocode Operation

num_active ← GetPatternLength(pattern, <T>)
for i = 0 to (VL / element_bits - 1):
  if i < num_active then
    Pd[i] ← 1
  else
    Pd[i] ← 0

Example

PTRUE p0.T

Encoding

Binary Layout

00100101

31:24

size

23:22

01100

21:17

111000

15:10

pattern

9:5

3:0

Format SVE Predicate

Opcode 0x2518E000

Extension SVE

Operands

Pd
Destination predicate register (SVE)
pattern
Pattern (e.g., VL1, VL2)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2518E000	PTRUE <Pd>.<T>{, <pattern>}		A64		00100101 \| size \| 01100 \| 0 \| 111000 \| pattern \| 0 \| Pd
0x25207810	PTRUE <PNd>.<T>		A64		00 \| 100101 \| size \| 100000011110 \| 000001 \| 0 \| PNd

Description

Set elements of the destination predicate to true if the element number satisfies the named predicate constraint, or to false otherwise. If the constraint specifies more elements than are available at the current vector length then all elements of the destination predicate are set to false. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception. Does not set the condition flags.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
integer count = DecodePredCount(pat, esize);
bits(PL) result;
constant integer psize = esize DIV 8;

for e = 0 to elements-1
    bit pbit = if e < count then '1' else '0';
    Elem[result, e, psize] = ZeroExtend(pbit, psize);

if setflags then
    PSTATE.<N,Z,C,V> = PredTest(result, result, esize);
P[d, PL] = result;