orr

SVE Bitwise OR (Predicated)

ORR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Bitwise OR of two vectors under predicate.

Details

The SVE Bitwise OR instruction bitwise OR of two vectors under predicate.

Pseudocode Operation

Zdn ← Pg OR Zm

Example

ORR z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout
00000100
sz
0
01101
Pg
Zm
Zdn
 
Format SVE Logic
Opcode 0x040D0000
Extension SVE

Operands

  • Zdn
    Combined destination/source scalable vector register (SVE)
  • Pg
    Mask
  • Zm
    Second source scalable vector register (SVE)